Abstract: A semiconductor integrated circuit including a waveform shaping circuit is provided. The waveform shaping circuit receives a signal. The waveform shaping circuit operates with a first inductance value in a first period. During the first period, a rising edge or a falling edge of a waveform of the signal is enhanced. The waveform shaping circuit operates with a second inductance value in a second period. During the second period, the rising or falling edges of the waveform is not enhanced. The first inductance value is larger than the second inductance value.

Abstract: A semiconductor integrated circuit including a waveform shaping circuit is provided. The waveform shaping circuit receives a signal. The waveform shaping circuit operates with a first inductance value in a first period. During the first period, a rising edge or a falling edge of a waveform of the signal is enhanced. The waveform shaping circuit operates with a second inductance value in a second period. During the second period, the rising or falling edges of the waveform is not enhanced. The first inductance value is larger than the second inductance value.

Abstract: According to one embodiment, in a semiconductor integrated circuit, a determination circuit is configured to generate first transition information, second transition information and phase determination information, with respect to a signal level of a modulation signal. The first transition information indicates a state of a first transition edge of transition between a first signal level and a second signal level. The second transition information indicates a state of a second transition edge of transition between a third signal level and a fourth signal level. The phase determination information indicates a result of a phase determination of a clock signal. An estimation circuit is configured to estimate a deviation between a timing of the first transition edge and a timing of the second transition edge according to the first transition information, the second transition information, and the phase determination information.

Abstract: A carrier leakage correction method for a quadrature modulator according to an embodiment includes inputting a test signal with a frequency fBB to a transmitter and up-converting the test signal with a frequency fL0 and down-converting with the frequency fL0. A frequency 2fBB component is detected in the down-converted test signal. One or a plurality of parameters of the transmitter is/are adjusted so as to reduce a magnitude of the detected frequency 2fBB component in the test signal.

Abstract: A carrier leakage correction method for a quadrature modulator according to an embodiment includes inputting a test signal with a frequency fBB to a transmitter and up-converting the test signal with a frequency fL0 and down-converting with the frequency fL0. A frequency 2fBB component is detected in the down-converted test signal. One or a plurality of parameters of the transmitter is/are adjusted so as to reduce a magnitude of the detected frequency 2fBB component in the test signal.

Abstract: A carrier leakage correction method for a quadrature modulator according to an embodiment includes inputting a test signal with a frequency fBB to a transmitter and up-converting the test signal with a frequency fL0 and down-converting with the frequency fL0. A frequency 2fBB component is detected in the down-converted test signal. One or a plurality of parameters of the transmitter is/are adjusted so as to reduce a magnitude of the detected frequency 2fBB component in the test signal.

Abstract: A carrier leakage correction method for a quadrature modulator according to an embodiment includes inputting a test signal with a frequency fBB to a transmitter and up-converting the test signal with a frequency fL0 and down-converting with the frequency fL0. A frequency 2fBB component is detected in the down-converted test signal. One or a plurality of parameters of the transmitter is/are adjusted so as to reduce a magnitude of the detected frequency 2fBB component in the test signal.

Abstract: According to an embodiment, a semiconductor integrated circuit includes an amplifier, an interference wave suppression unit, a coupler and a filter control circuit. The interference wave suppression unit includes a filter being controlled to be on or off. The filter is configured to suppress an interference wave component of an amplified signal to output the signal as an output signal when the filter is on. The coupler is configured to detect an input signal or the output signal. The filter control circuit controls the filter to be on when a signal level of a detection input signal or a detection output signal detected by the coupler is greater than or equal to a reference value, and controls the filter to be off when the signal level is smaller than the reference value, at arbitrary determination timing in a period of time between a transmission and a reception.

Abstract: According to an embodiment, a semiconductor integrated circuit includes an amplifier, an interference wave suppression unit, a coupler and a filter control circuit. The interference wave suppression unit includes a filter being controlled to be on or off. The filter is configured to suppress an interference wave component of an amplified signal to output the signal as an output signal when the filter is on. The coupler is configured to detect an input signal or the output signal. The filter control circuit controls the filter to be on when a signal level of a detection input signal or a detection output signal detected by the coupler is greater than or equal to a reference value, and controls the filter to be off when the signal level is smaller than the reference value, at arbitrary determination timing in a period of time between a transmission and a reception.

Abstract: A semiconductor integrated circuit device comprising a linearizer that has a plurality of switchable first gain characteristics, the linearizer switching to the first gain characteristic to generate an intermediate signal from an input signal by using the switched first gain characteristic, and outputting the intermediate signal to a circuit having a second gain characteristic, wherein the linearizer includes: a linearization unit that has at least one of first rectifier, and linearizes the input signal; and a linearization reducing unit that has a plurality of second rectifiers having polarity opposite to polarity of the first rectifier and a first switching unit selecting at least one of the second rectifiers based on a control signal, the linearization reducing unit being connected in parallel to the linearization unit and reducing linearization of the input signal by the linearization unit.

Abstract: A semiconductor device, has a main transistor that is a first-conductivity-type MOS transistor and has the drain connected to a first potential; a first switch circuit that is connected between the source of said main transistor and a second potential; a dummy transistor that is a first-conductivity-type MOS transistor whose source serves also as the source of said main transistor; and a second switch circuit that is connected between the drain of said dummy transistor and said first potential or said second potential.

Abstract: A semiconductor integrated circuit device comprising a linearizer that has a plurality of switchable first gain characteristics, the linearizer switching to the first gain characteristic to generate an intermediate signal from an input signal by using the switched first gain characteristic, and outputting the intermediate signal to a circuit having a second gain characteristic, wherein the linearizer includes: a linearization unit that has at least one of first rectifier, and linearizes the input signal; and a linearization reducing unit that has a plurality of second rectifiers having polarity opposite to polarity of the first rectifier and a first switching unit selecting at least one of the second rectifiers based on a control signal, the linearization reducing unit being connected in parallel to the linearization unit and reducing linearization of the input signal by the linearization unit.

Abstract: Embodiments described a semiconductor integrated circuit includes: a first coil and a second coil which have a mutual coupling and are connected in parallel to each other; a third coil connected in series to the first coil and the second coil; a first capacitor connected in parallel to the first coil; a second capacitor connected in parallel to the second coil; a first input terminal connected to an end of the first coil and an end of the first capacitor; a second input terminal connected to an end of the second coil and an end of the second capacitor; and an input-signal supplying portion configured to supply input signals of opposite phases to the first input terminal and the second input terminal, respectively.

Abstract: A semiconductor device, has a main transistor that is a first-conductivity-type MOS transistor and has the drain connected to a first potential; a first switch circuit that is connected between the source of said main transistor and a second potential; a dummy transistor that is a first-conductivity-type MOS transistor whose source serves also as the source of said main transistor; and a second switch circuit that is connected between the drain of said dummy transistor and said first potential or said second potential.

Abstract: A semiconductor device, has a main transistor that is a first-conductivity-type MOS transistor and has the drain connected to a first potential; a first switch circuit that is connected between the source of said main transistor and a second potential; a dummy transistor that is a first-conductivity-type MOS transistor whose source serves also as the source of said main transistor; and a second switch circuit that is connected between the drain of said dummy transistor and said first potential or said second potential.

Abstract: A semiconductor device, has a main transistor that is a first-conductivity-type MOS transistor and has the drain connected to a first potential; a first switch circuit that is connected between the source of said main transistor and a second potential; a dummy transistor that is a first-conductivity-type MOS transistor whose source serves also as the source of said main transistor; and a second switch circuit that is connected between the drain of said dummy transistor and said first potential or said second potential.