Abstract: A method of designing a layout of a semiconductor integrated circuit having a hard macro includes acquiring a condition for permitting wirings with respect to a given region within the hard macro, and searching a passing wiring that passes through the given region among the wirings that are arranged on the semiconductor integrated circuit. The method further includes allowing a normal passing wiring that satisfies the condition to pass through the hard macro, and wiring a defaulting passing wiring that does not satisfy the condition so as to bypass the hard macro among the searched passing wirings.

Abstract: A method of designing a layout of a semiconductor integrated circuit having a hard macro includes acquiring a condition for permitting wirings with respect to a given region within the hardmacro, and searching a passing wiring that passes through the given region among the wirings that are arranged 6n the semiconductor integrated circuit. The method further includes allowing a normal passing wiring that satisfies the condition to pass through the hardmacro, and wiring a defaulting passing wiring that does not satisfy the condition so as to bypass the hard macro among the searched passing wirings.

Abstract: A semiconductor device includes a logic circuit section having a plurality of logic circuits and configured to achieve a predetermined logical function; and a probing circuit connected with the logic circuit section. The probing circuit is not related to the predetermined logical function and comprises a diffusion layer used in a LVP (Laser Voltage Probing) method.