Abstract: A reconfigurable logical circuit includes a data processing unit; a memory in which plural combinations of configuration control bits are stored; and a selector unit that selectively switches the plural combinations of configuration control bits stored in the memory and supplies a selected one of the plural combinations of configuration control bits to the data processing unit to reconfigure processing contents of the data processing unit.

Abstract: An image processing apparatus includes an image processing block configured to encode each of plural data strings by using the number of common run lengths which are common to the plural data strings as run information of identical pixel values which are consecutive in each of the plural data strings.

Abstract: An image processing apparatus includes an image processing block configured to encode each of plural data strings by using the number of common run lengths which are common to the plural data strings as run information of identical pixel values which are consecutive in each of the plural data strings.

Abstract: A reconfigurable logical circuit includes a data processing unit; a memory in which plural combinations of configuration control bits are stored; and a selector unit that selectively switches the plural combinations of configuration control bits stored in the memory and supplies a selected one of the plural combinations of configuration control bits to the data processing unit to reconfigure processing contents of the data processing unit.

Abstract: An image processing apparatus includes a determiner that determines an array state of plural pixels to be collectively processed with a processing frame being a processing unit of image processing; and a matching unit that causes the plural pixels of image data to be in a data format matching with the processing frame by correction in accordance with the array state.

Abstract: A data processing apparatus includes a preprocessing section that causes an input data column to serve as a first determination data column and obtains a second determination data column by delaying the input data column and obtains a processing data column by delaying the input data column by an amount larger than an amount by which the input data column is delayed in order to obtain the second determination data column and a controller that controls, by using the first determination data column and the second determination data column as indices, an operation performed by a FIFO memory for outputting the processing data column, which has been input to the FIFO memory.

Abstract: A data processing apparatus includes a preprocessing section that causes an input data column to serve as a first determination data column and obtains a second determination data column by delaying the input data column and obtains a processing data column by delaying the input data column by an amount larger than an amount by which the input data column is delayed in order to obtain the second determination data column and a controller that controls, by using the first determination data column and the second determination data column as indices, an operation performed by a FIFO memory for outputting the processing data column, which has been input to the FIFO memory.

Abstract: An image processing apparatus includes a determiner that determines an array state of plural pixels to be collectively processed with a processing frame being a processing unit of image processing; and a matching unit that causes the plural pixels of image data to be in a data format matching with the processing frame by correction in accordance with the array state.

Abstract: A data decompressing device includes an effective code length detector and a determining unit. The detector detects an effective code length of an initial portion of compressed image data to be decompressed, and supplies the detected effective code length to a decompressing unit to decompress data having the effective code length from a head of the image data. The determining unit determines whether or not the initial portion of the image data corresponds to a specific pattern in which a block end code follows a code representing a specific DC difference value, and if having determined that the initial portion of the image data corresponds to the specific pattern, notifies the decompressing unit of the detection of the specific pattern without waiting for the detection of the effective code length, to allow the decompressing unit to output a predetermined decompression result corresponding to the specific DC difference value.

Abstract: A data decompressing device includes an effective code length detector and a determining unit. The detector detects an effective code length of an initial portion of compressed image data to be decompressed, and supplies the detected effective code length to a decompressing unit to decompress data having the effective code length from a head of the image data. The determining unit determines whether or not the initial portion of the image data corresponds to a specific pattern in which a block end code follows a code representing a specific DC difference value, and if having determined that the initial portion of the image data corresponds to the specific pattern, notifies the decompressing unit of the detection of the specific pattern without waiting for the detection of the effective code length, to allow the decompressing unit to output a predetermined decompression result corresponding to the specific DC difference value.

Abstract: An information processing apparatus includes a rendering processor that renders a plurality of objects on a page in a parallel process, an overlap determiner that determines a plurality of objects overlapping each other in accordance with coordinate information of each object on the page and acquires coordinate information of an overlap area between the objects, a timing controller that controls a timing of the rendering of each object in the parallel process of the rendering processor in accordance with the coordinate information of the overlap area, and a renderer that renders a lower-layer object in the overlap area in accordance with timing information generated by the timing controller prior to rendering an upper-layer object on the lower-layer object in a superimpose fashion.

Abstract: An image processing apparatus includes: a determining unit determining, in image data including packs each including pixels and serving as a unit, a monotonic pack including pixels equal to a precedently image-processed preceding pixel and a normal pack other than the monotonic pack; a pixel row forming unit forming a pixel row including aligned pixels of the normal pack, while deleting the pixels of the monotonic pack; a pixel row processing unit processing the formed pixel row by inputting the pixel row to an image processing unit; and a supplementing unit supplementing an image processing result of the pixel row output from the image processing unit with, as an image processing result of the deleted pixels of the monotonic pack, a result of image processing by the image processing unit on the preceding pixel of the normal pack, to thereby obtain an image processing result of the image data.

Abstract: An image data decoding device includes a determination unit, a first pixel value generating unit, and a second pixel value generating unit. The determination unit receives compressed image data including information of one DC component, information of frequency components and a block end code for each block of an image as a result of frequency analysis and determines whether the block consists of the DC component and the block end code. The first pixel value generating unit performs inverse operation to the frequency analysis to generate pixel values of the block when the block is determined as not consisting of the DC component and the block end code. The second pixel value generating unit generates one and the same pixel value for all pixels of each block based on information of the DC component when the block is determined as consisting of the DC component and block end code.

Abstract: An information processing apparatus includes a rendering processor that renders a plurality of objects on a page in a parallel process, an overlap determiner that determines a plurality of objects overlapping each other in accordance with coordinate information of each object on the page and acquires coordinate information of an overlap area between the objects, a timing controller that controls a timing of the rendering of each object in the parallel process of the rendering processor in accordance with the coordinate information of the overlap area, and a renderer that renders a lower-layer object in the overlap area in accordance with timing information generated by the timing controller prior to rendering an upper-layer object on the lower-layer object in a superimpose fashion.

Abstract: An image processing apparatus includes: a determining unit determining, in image data including packs each including pixels and serving as a unit, a monotonic pack including pixels equal to a precedently image-processed preceding pixel and a normal pack other than the monotonic pack; a pixel row forming unit forming a pixel row including aligned pixels of the normal pack, while deleting the pixels of the monotonic pack; a pixel row processing unit processing the formed pixel row by inputting the pixel row to an image processing unit; and a supplementing unit supplementing an image processing result of the pixel row output from the image processing unit with, as an image processing result of the deleted pixels of the monotonic pack, a result of image processing by the image processing unit on the preceding pixel of the normal pack, to thereby obtain an image processing result of the image data.

Abstract: It is assumed that the image data inputted are subjected to run-length compression and compressed encoding based on Huffman encoding. The first step configuration configured on a reconfigurable circuit includes run-length compression circuits 102a and 102b of two ways for parallel processing and FIFOs 108a and 108b which hold the output data from the circuits, respectively. For example, the data of odd pages are supplied to the run-length compression circuit 102a and the data of even pages are supplied to the run-length compression circuit 102b. After the compression processing proceeds, when at least one of the FIFOs 108a and 108b becomes full, the reconfigurable circuit is reconfigured into the second step configuration. In this configuration, the FIFOs 108a and 108b holding the compression results are left and two Huffman encoding circuits for encoding the data supplied from these FIFOs are included.

Abstract: An image data decoding device includes a determination unit, a first pixel value generating unit, and a second pixel value generating unit. The determination unit receives compressed image data including information of one DC component, information of frequency components and a block end code for each block of an image as a result of frequency analysis and determines whether the block consists of the DC component and the block end code. The first pixel value generating unit performs inverse operation to the frequency analysis to generate pixel values of the block when the block is determined as not consisting of the DC component and the block end code. The second pixel value generating unit generates one and the same pixel value for all pixels of each block based on information of the DC component when the block is determined as consisting of the DC component and block end code.

Abstract: It is assumed that the image data inputted are subjected to run-length compression and compressed encoding based on Huffman encoding. The first step configuration configured on a reconfigurable circuit includes run-length compression circuits 102a and 102b of two ways for parallel processing and FIFOs 108a and 108b which hold the output data from the circuits, respectively. For example, the data of odd pages are supplied to the run-length compression circuit 102a and the data of even pages are supplied to the run-length compression circuit 102b. After the compression processing proceeds, when at least one of the FIFOs 108a and 108b becomes full, the reconfigurable circuit is reconfigured into the second step configuration. In this configuration, the FIFOs 108a and 108b holding the compression results are left and two Huffman encoding circuits for encoding the data supplied from these FIFOs are included.

Abstract: An image processing device that executes high speed overwriting of an input image with one or more partial images. A processing prediction unit judges whether overwriting is completed on all the partial images held in a small area buffer. If overwriting is completed, the overwritten partial image is compressed by an encoding unit, and the coded image is stored in a compact page memory. If overwriting is not completed, the uncompressed partial image is stored in the compact page memory. The uncompressed partial image is read from the compact page memory and is fed back to the overwriting unit through an output switch unit. The coded image stored in the compact page memory is sent to a decoding unit through the output switch unit, and is decoded to be outputted as an output image.