Patents by Inventor Mitul B. Modi
Mitul B. Modi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10910314Abstract: Disclosed is a microelectronics package. The microelectronics package may include a reference plane, a signal routing layer, a dielectric layer, and a conductive layer. The signal routing layer may include a plurality of signal routing traces. The dielectric layer may be located adjacent to the signal routing layer. The conductive layer may be applied to the dielectric layer such that the dielectric layer is located in between the signal routing layer and the conductive layer. The conductive layer may be in electrical communication with the reference plane.Type: GrantFiled: December 12, 2019Date of Patent: February 2, 2021Assignee: Intel CorporationInventors: Li-Sheng Weng, Chung-Hao Joseph Chen, Emile Davies-Venn, Kemal Aygun, Mitul B. Modi
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Patent number: 10763220Abstract: Discussed generally herein are methods and devices including or providing an electromagnetic interference (EMI) shielding. A device can include substrate including electrical connection circuitry therein, ground circuitry on, or at least partially in the substrate, the ground circuitry at least partially exposed by a surface of the substrate, a die electrically connected to the connection circuitry and the ground circuitry, the die on the substrate, a conductive material on a die backside, and a conductive paste or one or more wires electrically connected to the ground circuitry and the conductive material.Type: GrantFiled: January 24, 2019Date of Patent: September 1, 2020Assignee: Intel CorporationInventors: Rajendra C. Dias, Mitul B. Modi
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Publication number: 20200118930Abstract: Disclosed is a microelectronics package. The microelectronics package may include a reference plane, a signal routing layer, a dielectric layer, and a conductive layer. The signal routing layer may include a plurality of signal routing traces. The dielectric layer may be located adjacent to the signal routing layer. The conductive layer may be applied to the dielectric layer such that the dielectric layer is located in between the signal routing layer and the conductive layer. The conductive layer may be in electrical communication with the reference plane.Type: ApplicationFiled: December 12, 2019Publication date: April 16, 2020Inventors: Li-Sheng Weng, Chung-Hao Joseph Chen, Emile Davies-Venn, Kemal Aygun, Mitul B. Modi
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Patent number: 10510667Abstract: Disclosed is a microelectronics package. The microelectronics package may include a reference plane, a signal routing layer, a dielectric layer, and a conductive layer. The signal routing layer may include a plurality of signal routing traces. The dielectric layer may be located adjacent to the signal routing layer. The conductive layer may be applied to the dielectric layer such that the dielectric layer is located in between the signal routing layer and the conductive layer. The conductive layer may be in electrical communication with the reference plane.Type: GrantFiled: December 21, 2016Date of Patent: December 17, 2019Assignee: Intel CorporationInventors: Li-Sheng Weng, Chung-Hao Joseph Chen, Emile Davies-Venn, Kemal Aygun, Mitul B. Modi
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Publication number: 20190157215Abstract: Discussed generally herein are methods and devices including or providing an electromagnetic interference (EMI) shielding. A device can include substrate including electrical connection circuitry therein, ground circuitry on, or at least partially in the substrate, the ground circuitry at least partially exposed by a surface of the substrate, a die electrically connected to the connection circuitry and the ground circuitry, the die on the substrate, a conductive material on a die backside, and a conductive paste or one or more wires electrically connected to the ground circuitry and the conductive material.Type: ApplicationFiled: January 24, 2019Publication date: May 23, 2019Inventors: Rajendra C. Dias, Mitul B. Modi
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Patent number: 10229887Abstract: Discussed generally herein are methods and devices including or providing an electromagnetic interference (EMI) shielding. A device can include substrate including electrical connection circuitry therein, ground circuitry on, or at least partially in the substrate, the ground circuitry at least partially exposed by a surface of the substrate, a die electrically connected to the connection circuitry and the ground circuitry, the die on the substrate, a conductive material on a die backside, and a conductive paste or one or more wires electrically connected to the ground circuitry and the conductive material.Type: GrantFiled: March 31, 2016Date of Patent: March 12, 2019Assignee: Intel CorporationInventors: Rajendra C. Dias, Mitul B. Modi
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Publication number: 20180174972Abstract: Disclosed is a microelectronics package. The microelectronics package may include a reference plane, a signal routing layer, a dielectric layer, and a conductive layer. The signal routing layer may include a plurality of signal routing traces. The dielectric layer may be located adjacent to the signal routing layer. The conductive layer may be applied to the dielectric layer such that the dielectric layer is located in between the signal routing layer and the conductive layer. The conductive layer may be in electrical communication with the reference plane.Type: ApplicationFiled: December 21, 2016Publication date: June 21, 2018Inventors: Li-Sheng Weng, Chung-Hao Joseph Chen, Emile Davies-Venn, Kemal Aygun, Mitul B. Modi
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Publication number: 20180166363Abstract: Semiconductor packages with electromagnetic interference (EMI) shielding structures and a method of manufacture therefor is disclosed. In some aspects, a shielding structure can serve as an enclosure formed by conductive material or by a mesh of such material that can be used to block electric fields emanating from one or more electronic components enclosed by the shielding structure at a global package level or local and/or compartment package level for semiconductor packages. In one embodiment, wire and/or ribbon bonding can be used to fabricate the shielding structure. For example, one or more wire and/or ribbon bonds can go from a connecting ground pad on one side of the package to a connecting ground pad on the other side of the package. This can be repeated multiple times at a pre-determined pitch necessary to meet the electrical requirements for shielding, e.g. less than or equal to approximately one half the wavelength of radiation generated by the electronic components being shielded.Type: ApplicationFiled: April 1, 2016Publication date: June 14, 2018Inventors: Joshua D. Heppner, Mitul B. Modi
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Publication number: 20170287846Abstract: Discussed generally herein are methods and devices including or providing an electromagnetic interference (EMI) shielding. A device can include substrate including electrical connection circuitry therein, ground circuitry on, or at least partially in the substrate, the ground circuitry at least partially exposed by a surface of the substrate, a die electrically connected to the connection circuitry and the ground circuitry, the die on the substrate, a conductive material on a die backside, and a conductive paste or one or more wires electrically connected to the ground circuitry and the conductive material.Type: ApplicationFiled: March 31, 2016Publication date: October 5, 2017Inventors: Rajendra C. Dias, Mitul B. Modi
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Publication number: 20170287847Abstract: Apparatus and methods are provided for an integrated circuit package that includes an integrated EMI shield. In an example, an integrated circuit package can include an integrated circuit mounted to a substrate via connections on the bottom surface of the integrated circuit, a conductive fence surrounding side surfaces of the integrated circuit, a conductive film coupled to the conductive fence, the film located above a top surface of the integrated circuit and coextensive with a footprint defined by the conductive fence.Type: ApplicationFiled: April 1, 2016Publication date: October 5, 2017Inventors: Rajendra C. Dias, Robert L. Sankman, Joshua D. Heppner, Mitul B. Modi, Yoshihiro Tomita
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Publication number: 20170250145Abstract: An electric device and method of fabrication of that electric device is disclosed. The electric device includes one or more electrical devices attached to a substrate. The electric device further includes one or more grounding pads attached to the substrate. The electric device further includes a perforated conductive material placed on the substrate. The electric device further includes a molding compound deposited to cover the perforated conductive material, the one or more devices, and the one or more grounding pads.Type: ApplicationFiled: May 15, 2017Publication date: August 31, 2017Inventors: Rajendra C. Dias, Joshua D. Heppner, Mitul B. Modi, Anna M. Prakash
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Patent number: 9704811Abstract: An electric device and method of fabrication of that electric device is disclosed. The electric device includes one or more electrical devices attached to a substrate. The electric device further includes one or more grounding pads attached to the substrate. The electric device further includes a perforated conductive material placed on the substrate. The electric device further includes a molding compound deposited to cover the perforated conductive material, the one or more devices, and the one or more grounding pads.Type: GrantFiled: December 22, 2015Date of Patent: July 11, 2017Assignee: Intel CorporationInventors: Rajendra C. Dias, Joshua D Heppner, Mitul B Modi, Anna M. Prakash
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Publication number: 20170179040Abstract: An electric device and method of fabrication of that electric device is disclosed. The electric device includes one or more electrical devices attached to a substrate. The electric device further includes one or more grounding pads attached to the substrate. The electric device further includes a perforated conductive material placed on the substrate. The electric device further includes a molding compound deposited to cover the perforated conductive material, the one or more devices, and the one or more grounding pads.Type: ApplicationFiled: December 22, 2015Publication date: June 22, 2017Inventors: Rajendra C. Dias, Joshua D. Heppner, Mitul B. Modi, Anna M. Prakash
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Patent number: 9516752Abstract: An underfill device and method have been are provided. Advantages of devices and methods shown include dissipation of stresses at an interface between components such as a chip package and an adjacent circuit board. Another advantage includes faster manufacturing time and ease of manufacture using underfill devices and methods shown. An underfill assembly can be pre made with conductive structures included within the underfill assembly. Steps such as flowing epoxy and curing can be eliminated or performed concurrently with other manufacturing steps.Type: GrantFiled: March 18, 2013Date of Patent: December 6, 2016Assignee: Intel CorporationInventors: Patricia A Brusso, Mitul B Modi, Carolyn R. McCormick, Ruben Cadena, Sankara J Subramanian, Edward L. Martin
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Publication number: 20130208411Abstract: An underfill device and method have been are provided. Advantages of devices and methods shown include dissipation of stresses at an interface between components such as a chip package and an adjacent circuit board. Another advantage includes faster manufacturing time and ease of manufacture using underfill devices and methods shown. An underfill assembly can be pre made with conductive structures included within the underfill assembly. Steps such as flowing epoxy and curing can be eliminated or performed concurrently with other manufacturing steps.Type: ApplicationFiled: March 18, 2013Publication date: August 15, 2013Inventors: Patricia A. Brusso, Mitul B. Modi, Carolyn R. McCormick, Ruben Cadena, Sankara J. Subramanian, Edward L. Martin
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Patent number: 8399291Abstract: An underfill device and method have been are provided. Advantages of devices and methods shown include dissipation of stresses at an interface between components such as a chip package and an adjacent circuit board. Another advantage includes faster manufacturing time and ease of manufacture using underfill devices and methods shown. An underfill assembly can be pre made with conductive structures included within the underfill assembly. Steps such as flowing epoxy and curing can be eliminated or performed concurrently with other manufacturing steps.Type: GrantFiled: June 29, 2005Date of Patent: March 19, 2013Assignee: Intel CorporationInventors: Patricia A Brusso, Mitul B Modi, Carolyn R. McCormick, Ruben Cadena, Sankara J Subramanian, Edward L. Martin
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Patent number: 7633142Abstract: An IC package is disclosed that comprises a core region disposed between upper and lower build-up layer regions. In one embodiment, the core region comprises a low modulus material. In an alternative embodiment the core region comprises a medium modulus material. In an alternative embodiment, the core material is selected based upon considerations such as it modulus, its coefficient of thermal expansion, and/or the resulting total accumulated strain. In an alternative embodiment, boundaries with respect to the softness of the core material are established be considering the reflective density in opposing conductive build-up layers above and below the core region.Type: GrantFiled: October 26, 2007Date of Patent: December 15, 2009Assignee: Intel CorporationInventors: Mitul B. Modi, Patricia A. Brusso, Ruben Cadena, Carolyn R. McCormick, Sankara J. Subramanian
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Patent number: 7352061Abstract: An IC package is disclosed that comprises a core region disposed between upper and lower build-up layer regions. In one embodiment, the core region comprises a low modulus material. In an alternative embodiment the core region comprises a medium modulus material. In an alternative embodiment, the core material is selected based upon considerations such as its modulus, its coefficient of thermal expansion, and/or the resulting total accumulated strain. In an alternative embodiment, boundaries with respect to the softness of the core material are established by considering the relative density in opposing conductive build-up layers above and below the core region.Type: GrantFiled: May 20, 2005Date of Patent: April 1, 2008Assignee: Intel CorporationInventors: Mitul B. Modi, Patricia A. Brusso, Ruben Cadena, Carolyn R. McCormick, Sankara J. Subramanian