Patents by Inventor Mituru Maeda

Mituru Maeda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8891688
    Abstract: A no signal period detecting unit (10) detects a no signal period in which no receiver signal is received. A capture unit (7) captures a synchronous timing of the receiver signal on the basis of a correlation value which is worked out by a delayed correlation computing unit (6). Further, the capture unit (7) cancels the capture of the synchronous timing in the case where this no signal period is detected by the no signal period detecting unit (10).
    Type: Grant
    Filed: July 21, 2010
    Date of Patent: November 18, 2014
    Assignee: Panasonic Corporation
    Inventors: Naoki Umeda, Mituru Maeda
  • Patent number: 8831152
    Abstract: The present invention provides a delay detector circuit that delivers performance at low cost and can reduce power consumption, and a receiver apparatus that uses this delay detector circuit. The delay detector circuit according to the present invention performs a part of decoding processing for decoding data transmitted by a transmitter apparatus based on a received wave of a two-phase modulation method. The receiver apparatus according to the present invention uses the delay detector circuit described above. Therefore the delay detector circuit and receiver apparatus of the present invention deliver performance at low cost and can reduce power consumption.
    Type: Grant
    Filed: July 8, 2010
    Date of Patent: September 9, 2014
    Assignee: Panasonic Corporation
    Inventors: Naoki Umeda, Mituru Maeda
  • Patent number: 8744019
    Abstract: The present invention provides a delay detector circuit that delivers performance at low cost and can reduce power consumption, and a receiver apparatus that uses this delay detector circuit. The delay detector circuit according to the present invention performs a part of the decoding processing for decoding data transmitted by a transmitter apparatus based on a received wave. The receiver apparatus according to the present invention uses the delay detector circuit described above. Therefore the delay detector circuit and receiver apparatus of the present invention deliver performance at low cost and can reduce power consumption.
    Type: Grant
    Filed: July 6, 2010
    Date of Patent: June 3, 2014
    Assignee: Panasonic Corporation
    Inventors: Naoki Umeda, Mituru Maeda
  • Publication number: 20120307943
    Abstract: Ano signal period detecting unit (10) detects a no signal period in which no receiver signal is received. A capture unit (7) captures a synchronous timing of the receiver signal on the basis of a correlation value which is worked out by a delayed correlation computing unit (6). Further, the capture unit (7) cancels the capture of the synchronous timing in the case where this no signal period is detected by the no signal period detecting unit (10).
    Type: Application
    Filed: July 21, 2010
    Publication date: December 6, 2012
    Applicant: PANASONIC CORPORATION
    Inventors: Naoki Umeda, Mituru Maeda
  • Publication number: 20120294397
    Abstract: The present invention provides a delay detector circuit that delivers performance at low cost and can reduce power consumption, and a receiver apparatus that uses this delay detector circuit. The delay detector circuit according to the present invention performs a part of the decoding processing for decoding data transmitted by a transmitter apparatus based on a received wave. The receiver apparatus according to the present invention uses the delay detector circuit described above. Therefore the delay detector circuit and receiver apparatus of the present invention deliver performance at low cost and can reduce power consumption.
    Type: Application
    Filed: July 6, 2010
    Publication date: November 22, 2012
    Applicant: PANASONIC CORPORATION
    Inventors: Naoki Umeda, Mituru Maeda
  • Publication number: 20120294394
    Abstract: The present invention provides a delay detector circuit that delivers performance at low cost and can reduce power consumption, and a receiver apparatus that uses this delay detector circuit. The delay detector circuit according to the present invention performs a part of decoding processing for decoding data transmitted by a transmitter apparatus based on a received wave of a two-phase modulation method. The receiver apparatus according to the present invention uses the delay detector circuit described above. Therefore the delay detector circuit and receiver apparatus of the present invention deliver performance at low cost and can reduce power consumption.
    Type: Application
    Filed: July 8, 2010
    Publication date: November 22, 2012
    Applicant: PANASONIC CORPORATION
    Inventors: Naoki Umeda, Mituru Maeda