Patents by Inventor Miwa Ichiryu

Miwa Ichiryu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device including a first wiring having a bending portion a via
    Patent number: 8841774
    Abstract: A first wiring (1) has a bending portion (2), a first wiring region (1a) extending from the bending portion (2) in the X direction, and a second wiring region (1b) extending from the bending portion (2) in the Y direction. A via (3) is formed under the wiring (1). The via (3) is formed so as not to overlap with a region of the bending portion (2) in the first wiring region (1a). The length of the via (3) in the X direction (x) is longer than the length thereof in the Y direction (y) and both ends of the via (3) in the Y direction overlap with both ends of the first wiring region (1a) in the Y direction.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: September 23, 2014
    Assignee: Panasonic Corporation
    Inventors: Miwa Ichiryu, Hiroyuki Uehara, Hidetoshi Nishimura
  • Semiconductor device including a first wiring having a bending portion and a via including the bending portion
    Patent number: 8426978
    Abstract: A first wiring (1) has a bending portion (2), a first wiring region (1a) extending from the bending portion (2) in the X direction, and a second wiring region (1b) extending from the bending portion (2) in the Y direction. A via (3) is formed under the wiring (1). The via (3) is formed so as not to overlap with a region of the bending portion (2) in the first wiring region (1a). The length of the via (3) in the X direction (x) is longer than the length thereof in the Y direction (y) and both ends of the via (3) in the Y direction overlap with both ends of the first wiring region (1a) in the Y direction.
    Type: Grant
    Filed: January 14, 2010
    Date of Patent: April 23, 2013
    Assignee: Panasonic Corporation
    Inventors: Miwa Ichiryu, Hiroyuki Uehara, Hidetoshi Nishimura
  • SEMICONDUCTOR DEVICE, BASIC CELL, AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
    Publication number: 20110006439
    Abstract: A first wiring (1) has a bending portion (2), a first wiring region (1a) extending from the bending portion (2) in the X direction, and a second wiring region (1b) extending from the bending portion (2) in the Y direction. A via (3) is formed under the wiring (1). The via (3) is formed so as not to overlap with a region of the bending portion (2) in the first wiring region (1a). The length of the via (3) in the X direction (x) is longer than the length thereof in the Y direction (y) and both ends of the via (3) in the Y direction overlap with both ends of the first wiring region (1a) in the Y direction.
    Type: Application
    Filed: January 14, 2010
    Publication date: January 13, 2011
    Inventors: Miwa Ichiryu, Hiroyuki Uehara, Hidetoshi Nishimura
  • CELL, STANDARD CELL, STANDARD CELL LIBRARY, A PLACEMENT METHOD USING STANDARD CELL, AND A SEMICONDUCTOR INTEGRATED CIRCUIT
    Publication number: 20090138840
    Abstract: A cell according to the present invention comprises a plurality of terminals capable of transmitting an input signal or an output signal and serving as a minimum unit in designing a semiconductor integrated circuit, wherein the plurality of terminals is located on routing grids lined in a Y direction which is a direction vertical to a power-supply wiring of the cell used in automatic placement & routing and has a shape extended in an X direction which is a direction in parallel with the power-supply wiring, more specifically such a shape that, for example, a longer-side dimension of the terminal is equal to “a routing grid interval in the X direction+a wiring width. According to the constitution, a cell area is reduced, which advantageously leads to the reduction of a chip area.
    Type: Application
    Filed: January 26, 2009
    Publication date: May 28, 2009
    Applicant: PANASONIC CORPORATION
    Inventors: Miwa Ichiryu, Toshiyuki Moriwaki, Tetsurou Toubou
  • Cell, standard cell, standard cell library, a placement method using standard cell, and a semiconductor integrated circuit
    Patent number: 7503026
    Abstract: A cell according to the present invention comprises a plurality of terminals capable of transmitting an input signal or an output signal and serving as a minimum unit in designing a semiconductor integrated circuit, wherein the plurality of terminals is located on routing grids lined in a Y direction which is a direction vertical to a power-supply wiring of the cell used in automatic placement & routing and has a shape extended in an X direction which is a direction in parallel with the power-supply wiring, more specifically such a shape that, for example, a longer-side dimension of the terminal is equal to “a routing grid interval in the X direction+a wiring width. According to the constitution, a cell area is reduced, which advantageously leads to the reduction of a chip area.
    Type: Grant
    Filed: December 19, 2005
    Date of Patent: March 10, 2009
    Assignee: Panasonic Corporation
    Inventors: Miwa Ichiryu, Toshiyuki Moriwaki, Tetsurou Toubou
  • Cell, standard cell, standard cell library, a placement method using standard cell, and a semiconductor integrated circuit
    Publication number: 20060136848
    Abstract: A cell according to the present invention comprises a plurality of terminals capable of transmitting an input signal or an output signal and serving as a minimum unit in designing a semiconductor integrated circuit, wherein the plurality of terminals is located on routing grids lined in a Y direction which is a direction vertical to a power-supply wiring of the cell used in automatic placement & routing and has a shape extended in an X direction which is a direction in parallel with the power-supply wiring, more specifically such a shape that, for example, a longer-side dimension of the terminal is equal to “a routing grid interval in the X direction+a wiring width. According to the constitution, a cell area is reduced, which advantageously leads to the reduction of a chip area.
    Type: Application
    Filed: December 19, 2005
    Publication date: June 22, 2006
    Inventors: Miwa Ichiryu, Toshiyuki Moriwaki, Tetsurou Toubou