Patents by Inventor Miwa Wake
Miwa Wake has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7586160Abstract: A semiconductor integrated circuit is provided in which a CMOS transistor is formed on a first conductivity type semiconductor film provided on a first conductivity type supporting substrate through an embedded insulating film. Second conductivity type source and drain regions are formed in the semiconductor film. The source region has an ultra-shallow high-density second conductivity type source extension region at a boundary with a channel region, a low-density second conductivity type source extension region under the ultra-shallow high-density second conductivity type source extension region, and a high-density second conductivity type source extension region under the low-density second conductivity type source extension region.Type: GrantFiled: June 26, 2007Date of Patent: September 8, 2009Assignee: Seiko Instuments Inc.Inventors: Miwa Wake, Yoshifumi Yoshida
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Patent number: 7351595Abstract: In a manufacturing method for a semiconductor device, a main body wafer having an interlayer insulating film is formed, and a monitor wafer on which a monitor element is formed is provided. Characteristics of the main body wafer are copied onto the monitor element by simultaneously processing the main body wafer and the monitor wafer through BPSG densification during formation of the interlayer insulating film. The characteristic of the monitor element is measured by checking a process influence of the monitor element. Manufacturing conditions are set in accordance with the process influence of the monitor element. Variations in electric characteristics of the main body wafer are reduced in accordance with the set manufacturing conditions.Type: GrantFiled: September 8, 2004Date of Patent: April 1, 2008Assignee: Seiko Instruments Inc.Inventors: Kazutoshi Ishii, Jun Osanai, Yuichiro Kitajima, Yukimasa Minami, Keisuke Uemura, Miwa Wake
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Patent number: 7335518Abstract: In a manufacturing method for a semiconductor device, a main body wafer is formed, and a monitor wafer on which a monitor element is formed is provided. Characteristics of the main body wafer are copied onto the monitor element by simultaneously processing the main body wafer and the monitor wafer. The characteristic of the monitor element is measured by checking a process influence of the monitor element. Manufacturing conditions are set in accordance with the process influence of the monitor element. Variations in electric characteristics of the main body wafer are reduced in accordance with the set manufacturing conditions.Type: GrantFiled: September 8, 2004Date of Patent: February 26, 2008Assignee: Seiko Instruments Inc.Inventors: Kazutoshi Ishii, Jun Osanai, Yuichiro Kitajima, Yukimasa Minami, Keisuke Uemura, Miwa Wake
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Publication number: 20070254426Abstract: Conventionally, when an electric potential of a supporting substrate is fixed, there arises a problem in that impact ions are generated even in the vicinity of embedded insulating film in the proximity of a drain due to generation of a parasitic transistor using the supporting substrate as a gate so as to be likely to cause a parasitic bipolar operation.Type: ApplicationFiled: June 26, 2007Publication date: November 1, 2007Inventors: Miwa Wake, Yoshifumi Yoshida
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Patent number: 7253048Abstract: A semiconductor integrated circuit has a CMOS transistor formed on a first conductivity type semiconductor film provided on a first conductivity type supporting substrate through an embedded insulating film. Thermal oxidation is conducted to form a LOCOS for element separation between transistors in the semiconductor film. A gate oxide film of a second conductivity type transistor is formed over the insulating film. A first conductivity type impurity region is formed between the gate oxide film and the embedded insulating film in a region where the second conductivity type transistor is to be formed. A first conductivity type impurity region having a higher density than that of the first conductivity type impurity region is formed in a middle depth portion of the semiconductor film serving as the proximal region to a drain in the first conductivity type impurity region.Type: GrantFiled: January 28, 2004Date of Patent: August 7, 2007Assignee: Seiko Instruments Inc.Inventors: Miwa Wake, Yoshifumi Yoshida
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Patent number: 7192790Abstract: A manufacturing method for a semiconductor device which is capable of manufacturing the semiconductor device with a high quality in high yields while reducing variations in electric characteristic is disclosed. The manufacturing method according to the present invention includes a main body wafer manufacturing process for manufacturing a wafer on which a semiconductor device to be completed as a product is formed and a monitor wafer manufacturing process for manufacturing a wafer on which a monitor element is formed, the processes sharing a monitoring step alone, the main body wafer manufacturing process including a variation reduction step, the monitor wafer manufacturing process including a quality check step and a condition setting step.Type: GrantFiled: September 8, 2004Date of Patent: March 20, 2007Assignee: Seiko Instruments Inc.Inventors: Kazutoshi Ishii, Jun Osanai, Yuichiro Kitajima, Yukimasa Minami, Keisuke Uemura, Miwa Wake
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Patent number: 7129099Abstract: A manufacturing method for a semiconductor device which is capable of manufacturing the semiconductor device with a high quality in high yields while reducing variations in electric characteristic is disclosed. The manufacturing method according to the present invention includes a main body wafer manufacturing process for manufacturing a wafer on which a semiconductor device to be completed as a product is formed and a monitor wafer manufacturing process for manufacturing a wafer on which a monitor element is formed, the processes sharing a monitoring step alone, the main body wafer manufacturing process including a variation reduction step, the monitor wafer manufacturing process including a quality check step and a condition setting step.Type: GrantFiled: September 8, 2004Date of Patent: October 31, 2006Assignee: Seiko Instruments Inc.Inventors: Kazutoshi Ishii, Jun Osanai, Yuichiro Kitajima, Yukimasa Minami, Keisuke Uemura, Miwa Wake
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Patent number: 7043328Abstract: A manufacturing method for a semiconductor device which is capable of manufacturing the semiconductor device with a high quality in high yields while reducing variations in electric characteristic is disclosed. The manufacturing method according to the present invention includes a main body wafer manufacturing process for manufacturing a wafer on which a semiconductor device to be completed as a product is formed and a monitor wafer manufacturing process for manufacturing a wafer on which a monitor element is formed, the processes sharing a monitoring step alone, the main body wafer manufacturing process including a variation reduction step, the monitor wafer manufacturing process including a quality check step and a condition setting step.Type: GrantFiled: September 8, 2004Date of Patent: May 9, 2006Assignee: Seiko Instruments Inc.Inventors: Kazutoshi Ishii, Jun Osanai, Yuichiro Kitajima, Yukimasa Minami, Keisuke Uemura, Miwa Wake
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Patent number: 6995055Abstract: A method of fabricating CMOS transistors of first and second conductivity types in an SOI substrate includes the steps of etching contact holes and alignment marks through the semiconductor and insulating films and into the support substrate of an SOI substrate, forming a thermal oxide film on the semiconductor layer inside the contact holes, forming back regions of the CMOS transistors in the substrate, forming a well regions of the CMOS transistors in the semiconductor film, forming a gate oxide film, gate electrodes, source regions, drain regions, and body regions, forming an interlayer insulating film, forming contacts of the source regions, drain regions, and body regions, forming openings in the interlayer insulating film over the contact holes, and forming wiring on the interlayer insulating film.Type: GrantFiled: February 7, 2003Date of Patent: February 7, 2006Assignee: Seiko Instruments Inc.Inventors: Yoshifumi Yoshida, Miwa Wake
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Publication number: 20050142673Abstract: A manufacturing method for a semiconductor device which is capable of manufacturing the semiconductor device with a high quality in high yields while reducing variations in electric characteristic is disclosed. The manufacturing method according to the present invention includes a main body wafer manufacturing process for manufacturing a wafer on which a semiconductor device to be completed as a product is formed and a monitor wafer manufacturing process for manufacturing a wafer on which a monitor element is formed, the processes sharing a monitoring step alone, the main body wafer manufacturing process including a variation reduction step, the monitor wafer manufacturing process including, a quality check step and a condition setting step.Type: ApplicationFiled: September 8, 2004Publication date: June 30, 2005Inventors: Kazutoshi Ishii, Jun Osanai, Yuichiro Kitajima, Yukimasa Minami, Keisuke Uemura, Miwa Wake
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Publication number: 20050130332Abstract: A manufacturing method for a semiconductor device which is capable of manufacturing the semiconductor device with a high quality in high yields while reducing variations in electric characteristic is disclosed. The manufacturing method according to the present invention includes a main body wafer manufacturing process for manufacturing a wafer on which a semiconductor device to be completed as a product is formed and a monitor wafer manufacturing process for manufacturing a wafer on which a monitor element is formed, the processes sharing a monitoring step alone, the main body wafer manufacturing process including a variation reduction step, the monitor wafer manufacturing process including a quality check step and a condition setting step.Type: ApplicationFiled: September 8, 2004Publication date: June 16, 2005Inventors: Kazutoshi Ishii, Jun Osanai, Yuichiro Kitajima, Yukimasa Minami, Keisuke Uemura, Miwa Wake
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Publication number: 20050124083Abstract: A manufacturing method for a semiconductor device which is capable of manufacturing the semiconductor device with a high quality in high yields while reducing variations in electric characteristic is disclosed. The manufacturing method according to the present invention includes a main body wafer manufacturing process for manufacturing a wafer on which a semiconductor device to be completed as a product is formed and a monitor wafer manufacturing process for manufacturing a wafer on which a monitor element is formed, the processes sharing a monitoring step alone, the main body wafer manufacturing process including a variation reduction step, the monitor wafer manufacturing process including a quality check step and a condition setting step.Type: ApplicationFiled: September 8, 2004Publication date: June 9, 2005Inventors: Kazutoshi Ishii, Jun Osanai, Yuichiro Kitajima, Yukimasa Minami, Keisuke Uemura, Miwa Wake
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Publication number: 20050124082Abstract: A manufacturing method for a semiconductor device which is capable of manufacturing the semiconductor device with a high quality in high yields while reducing variations in electric characteristic is disclosed. The manufacturing method according to the present invention includes a main body wafer manufacturing process for manufacturing a wafer on which a semiconductor device to be completed as a product is formed and a monitor wafer manufacturing process for manufacturing a wafer on which a monitor element is formed, the processes sharing a monitoring step alone, the main body wafer manufacturing process including a variation reduction step, the monitor wafer manufacturing process including a quality check step and a condition setting step.Type: ApplicationFiled: September 8, 2004Publication date: June 9, 2005Inventors: Kazutoshi Ishii, Jun Osanai, Yuichiro Kitajima, Yukimasa Minami, Keisuke Uemura, Miwa Wake
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Publication number: 20050124081Abstract: A manufacturing method for a semiconductor device which is capable of manufacturing the semiconductor device with a high quality in high yields while reducing variations in electric characteristic is disclosed. The manufacturing method according to the present invention includes a main body wafer manufacturing process for manufacturing a wafer on which a semiconductor device to be completed as a product is formed and a monitor wafer manufacturing process for manufacturing a wafer on which a monitor element is formed, the processes sharing a monitoring step alone, the main body wafer manufacturing process including a variation reduction step, the monitor wafer manufacturing process including a quality check step and a condition setting step.Type: ApplicationFiled: September 8, 2004Publication date: June 9, 2005Inventors: Kazutoshi Ishii, Jun Osanai, Yuichiro Kitajima, Yukimasa Minami, Keisuke Uemura, Miwa Wake
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Publication number: 20040191967Abstract: Conventionally, when an electric potential of a supporting substrate is fixed, there arises a problem in that impact ions are generated even in the vicinity of embedded insulating film in the proximity of a drain due to generation of a parasitic transistor using the supporting substrate as a gate so as to be likely to cause a parasitic bipolar operation.Type: ApplicationFiled: January 28, 2004Publication date: September 30, 2004Applicant: SEIKO INSTRUMENTS INC.Inventors: Miwa Wake, Yoshifumi Yoshida
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Patent number: 6740551Abstract: A semiconductor integrated circuit is provided in which a change in timing of a circuit or variation in a driving ability do not occur even if the potential of a support substrate is fixed.Type: GrantFiled: September 6, 2002Date of Patent: May 25, 2004Assignee: Seiko Instruments Inc.Inventors: Yoshifumi Yoshida, Miwa Wake
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Patent number: 6713325Abstract: Conventionally, when an electric potential of a supporting substrate is fixed, there arises a problem in that impact ions are generated even in the vicinity of embedded insulating film in the proximity of a drain due to generation of a parasitic transistor using the supporting substrate as a gate so as to be likely to cause a parasitic bipolar operation.Type: GrantFiled: October 9, 2002Date of Patent: March 30, 2004Assignee: Seiko Instruments Inc.Inventors: Miwa Wake, Yoshifumi Yoshida
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Publication number: 20030155615Abstract: To provide a semiconductor integrated circuit with a small change in characteristics and further with ideal subthreshold characteristics, in which an influence of a potential of a support substrate is suppressed.Type: ApplicationFiled: February 7, 2003Publication date: August 21, 2003Inventors: Yoshifumi Yoshida, Miwa Wake
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Publication number: 20030129792Abstract: Conventionally, when an electric potential of a supporting substrate is fixed, there arises a problem in that impact ions are generated even in the vicinity of embedded insulating film in the proximity of a drain due to generation of a parasitic transistor using the supporting substrate as a gate so as to be likely to cause a parasitic bipolar operation.Type: ApplicationFiled: October 9, 2002Publication date: July 10, 2003Inventors: Miwa Wake, Yoshifumi Yoshida
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Patent number: RE42223Abstract: Conventionally, when an electric potential of a supporting substrate is fixed, there arises a problem in that impact ions are generated even in the vicinity of embedded insulating film in the proximity of a drain due to generation of a parasitic transistor using the supporting substrate as a gate so as to be likely to cause a parasitic bipolar operation.Type: GrantFiled: March 28, 2006Date of Patent: March 15, 2011Assignee: Seiko Instruments Inc.Inventors: Miwa Wake, Yoshifumi Yoshida