Abstract: Based on a relative comparison of respective consumed powers of cells which are subjected to a layout, separation information on cells to be separated which are to be arranged in a spaced-apart manner from each other is generated by separation information generating means, and a layout is generated by layout generating means based on this separation information. Accordingly, it is no more necessary to rearrange cells or to form a layout of the entire circuit again after generating an initial layout. Furthermore, it is no more necessary to set wide spacing between wirings. Still furthermore, the occurrence of noise is prevented.

Abstract: The method for designing an integrated circuit device of the present invention includes the steps of: obtaining the number of operations by a functional simulation; determining a specification model based on the number of operations; determining an behavioral model corresponding to the specification model based on the number of operations per cycle required; determining a RTL model corresponding to the behavioral model based on the number of operations per cycle required; and obtaining design data corresponding to the RTL model for implementing the function.

Abstract: The method for designing an integrated circuit device of the present invention includes the steps of: obtaining the number of operations by a functional simulation; determining a specification model based on the number of operations; determining an behavioral model corresponding to the specification model based on the number of operations per cycle required; determining a RTL model corresponding to the behavioral model based on the number of operations per cycle required; and obtaining design data corresponding to the RTL model for implementing the function.

Abstract: Architecture design (AD), architecture floorplanning (AF), and transaction analysis (TA) are performed before transaction-analysis-based floorplanning (TF). Then, area estimation (CE) is performed on functional parts and connections before area-based floorplanning (CF) and area optimization (CO) are performed, and whether or not the area specifications area satisfied or not is validated (CR). Besides, power consumption estimation (PE) is performed to check whether or not the power consumption specifications are satisfied (PR). In the case of taking a parallelization approach to realize lower power consumption, parallelization design (PD) is performed. After the power consumption specifications are satisfied, power supply wiring/floorplanning is performed.

Abstract: A design technique considering a peak current is provided for high-level design of systems including LSIs. A hardware model representing the trade-off relationship between a leak current and performance is prepared in advance for functional units constituting the system. In the hardware model, the relationship between performance tpd and a source-drain leak current Pleak is described with a threshold voltage Vth as a parameter, for example. By referring to the trade-off relationship, design conditions for the functional units are determined under evaluation of the performance and power consumption of the entire system.

Abstract: A function information storage section of each of a plurality of IPs of a device stores a plurality of sets of correlations between the working voltage V and the processing time T required when operated at this voltage. The device also includes a system controller for controlling the operation of each IP. When the voltage exceeds a limitation at a certain time as a result of analysis, the working voltage of each IP is changed to fall within the limitation.

Abstract: A database, in which data is stored in a flexibly usable state, is provided for use in the design of an integrated circuit device, and a method for designing an integrated circuit device using such a database is also provided. A design environment includes: a virtual core database (VCDB), which is hierarchical design data storage; and a virtual core database management system (VCDBMS) as a control system. The VCDB includes architecture information and a VC cluster. The VC cluster includes: a specification VC for storing therein data at a specification level; an architecture VC for storing therein data at an architectural level; an RTL-VC for storing therein data at a register transfer level; and a performance index used for evaluating the performance of the respective VCs. By providing these VCs for respective layers, new VCs can be generated, data within the VCs can be modified and instances can be generated at the respective levels. As a result, the data can be used flexibly and recycled as well.

Abstract: In an integrated circuit device, when a net having many toggle counts exists in a circuit including blocks each having function modules, the circuit is changed to an equivalent circuit where the net is included inside a block. In the circuit, when the toggle counts of a function module in a block are especially many, a plurality of parallel blocks is provided in place of the block. When a plurality of pins of a block can be exchanged without changing the output value although the internal toggle counts of the block changes, the input pins are exchanged so that the internal toggle counts are less. Objects to be connected via a net having many toggle counts are given priority to be placed closer to each other in the floor plan.

Abstract: A database, in which data is stored in a flexibly usable state, is provided for use in the design of an integrated circuit device. And a method for designing an integrated circuit device using such a database is also provided. A design environment includes: a virtual core database (VCDB), which is hierarchical design data storage; and a virtual core database management system (VCDBMS) as a control system. The VCDB includes architecture information and a VC cluster. The VC cluster includes: a specification VC for storing thereon data at a specification level; an architecture VC for storing thereon data at an architectural level; an RTL-VC for storing thereon data at a register transfer level; and a performance index used for evaluating the performance of the respective VCs. By providing these VCs for respective layers, new VCs can be generated, data within the VCs can be modified and instances can be generated at the respective levels. As a result, the data can be used flexibly and recycled as well.

Abstract: A database, in which data is stored in a flexibly usable state, is provided for use in the design of an integrated circuit device. And a method for designing an integrated circuit device using such a database is also provided. A design environment includes: a virtual core database (VCDB), which is hierarchical design data storage; and a virtual core database management system (VCDBMS) as a control system. The VCDB includes architecture information and a VC cluster. The VC cluster includes: a specification VC for storing thereon data at a specification level; an architecture VC for storing thereon data at an architectural level; an RTL-VC for storing thereon data at a register transfer level; and a performance index used for evaluating the performance of the respective VCs. By providing these VCs for respective layers, new VCs can be generated, data within the VCs can be modified and instances can be generated at the respective levels. As a result, the data can be used flexibly and recycled as well.

Abstract: Based on a relative comparison of respective consumed powers of cells which are subjected to a layout, separation information on cells to be separated which are to be arranged in a spaced-apart manner from each other is generated by separation information generating means, and a layout is generated by layout generating means based on this separation information. Accordingly, it is no more necessary to rearrange cells or to form a layout of the entire circuit again after generating an initial layout. Furthermore, it is no more necessary to set wide spacing between wirings. Still furthermore, the occurrence of noise is prevented.

Abstract: Based on a relative comparison of respective consumed powers of cells which are subjected to a layout, separation information on cells to be separated which are to be arranged in a spaced-apart manner from each other is generated by separation information generating means, and a layout is generated by layout generating means based on this separation information. Accordingly, it is no more necessary to rearrange cells or to form a layout of the entire circuit again after generating an initial layout. Furthermore, it is no more necessary to set wide spacing between wirings. Still furthermore, the occurrence of noise is prevented.

Abstract: A function information storage section of each of a plurality of IPs of a device stores a plurality of sets of correlations between the working voltage V and the processing time T required when operated at this voltage. The device also includes a system controller for controlling the operation of each IP. When the voltage exceeds a limitation at a certain time as a result of analysis, the working voltage of each IP is changed to fall within the limitation.

Abstract: In a semiconductor integrated circuit, a CMOS logic circuit receives a voltage from a power-source line, while releasing a current through a ground line. A constant-voltage auxiliary circuit is disposed in parallel with the CMOS logic circuit. The constant-voltage auxiliary circuit receives an output signal from the CMOS logic circuit. The constant-voltage auxiliary circuit consumes power when the output signal from the CMOS logic circuit is stable to maintain a potential difference between the power-source line and the ground line at a specified voltage and halts power consumption when the output signal from the CMOS logic circuit is inverted, i.e., when the potential difference is decreasing, thereby suppressing the decrease of the potential difference. Accordingly, voltage fluctuations on the power-source line are suppressed.

Abstract: Architecture design (AD), architecture floorplanning (AF), and transaction analysis (TA) are performed before transaction-analysis-based floorplanning (TF). Then, area estimation (CE) is performed on functional parts and connections before area-based floorplanning (CF) and area optimization (CO) are performed, and whether or not the area specifications area satisfied or not is validated (CR). Besides, power consumption estimation (PE) is performed to check whether or not the power consumption specifications are satisfied (PR). In the case of taking a parallelization approach to realize lower power consumption, parallelization design (PD) is performed. After the power consumption specifications are satisfied, power supply wiring/floorplanning is performed.

Abstract: Logic circuits are experimentally automatically synthesized, and a representative line length of each fanout number is estimated on the basis of a net list resulting from the synthesis. The representative line length corresponds to a length of a line positioned at a center when plural lines are aligned in the order of their lengths (namely, a median line length WLmed(fn)). Furthermore, a standard deviation .sigma.med(fn) and a probability coefficient K(fn) of the deviation are calculated with regard to each fanout number on the basis of the net list. Then, a defined line length WL(fn) of each fanout number fn is calculated by using an expression, WL(fn) =WLmed(fn)+K(fn).multidot..sigma.med(fn). At this point, when there is a demand for design of an LSI having a high operation speed, the probability coefficient K(fn) is set at a small value, and when there is a demand for design of an LSI completed in a short period of time, the probability coefficient K(fn) is set at a large value.

Abstract: In a semiconductor integrated circuit, a CMOS logic circuit receives a voltage from a power-source line, while releasing a current through a ground line. A constant-voltage auxiliary circuit is disposed in parallel with the CMOS logic circuit. The constant-voltage auxiliary circuit receives an output signal from the CMOS logic circuit. The constant-voltage auxiliary circuit consumes power when the output signal from the CMOS logic circuit is stable to maintain a potential difference between the power-source line and the ground line at a specified voltage and halts power consumption when the output signal from the CMOS logic circuit is inverted, i.e., when the potential difference is decreasing, thereby suppressing the decrease of the potential difference. Accordingly, voltage fluctuations on the power-source line are suppressed.