Abstract: It is intended to provide net list creating method, net list creating device, and computer program thereof capable of creating net list of memory space by selecting optimum combination of memory macros and providing a control circuit for controlling and making the combination accessible as memory space from a previously registered library so as to realize required memory space. For realizing a target memory with a single memory macro by extending its word width, processing goes on to as follows: target word width of a target memory is larger than maximum macro word width of a memory macro (S5: YES); first word width ratio (WR1), target word width to maximum macro word width, is 2n and first bit width ratio (BR1), bit width of a target memory to bit width of memory macro which has maximum macro word width, is 2(?n) or smaller (S9: YES); a memory macro which has maximum macro word width is selected (S11); and a control circuit is selected from a control library (D3) previously provided after branch a.

Abstract: It is intended to provide net list creating method, net list creating device, and computer program thereof capable of creating net list of memory space by selecting optimum combination of memory macros and providing a control circuit for controlling and making the combination accessible as memory space from a previously registered library so as to realize required memory space. For realizing a target memory with a single memory macro by extending its word width, processing goes on to as follows: target word width of a target memory is larger than maximum macro word width of a memory macro (S5: YES); first word width ratio (WR1), target word width to maximum macro word width, is 2n and first bit width ratio (BR1), bit width of a target memory to bit width of memory macro which has maximum macro word width, is 2(?n) or smaller (S9: YES); a memory macro which has maximum macro word width is selected (S11); and a control circuit is selected from a control library (D3) previously provided after branch a.

Abstract: In a method of and an apparatus for designing a semiconductor integrated circuit device, which are capable of causing each waveform rounding to fall within a predetermined limit value without delay calculations at an early stage of the development of the semiconductor integrated circuit device, a wiring path resistance Rpath from an output terminal of a target circuit cell to a next-stage circuit cell and an allowable longest wiring resistance RtL drivable by the target circuit cell are compared. When Rpath is less than or equal to RtL (S4: YES), the sum Rtotal of resistances of wiring loads in a net and RtL are compared. If Rtotal is less than or equal to RtL (S5: YES), then the next-stage circuit cell is judged to be drivable within a predetermined waveform rounding limit value. When Rtotal is greater than RtL (S5: NO), an effective resistance Rw of each wiring load and an allowable longest wiring effective resistance RwL are compared.

Abstract: In a method of and an apparatus for designing a semiconductor integrated circuit device, which are capable of causing each waveform rounding to fall within a predetermined limit value without delay calculations at an early stage of the development of the semiconductor integrated circuit device, a wiring path resistance Rpath from an output terminal of a target circuit cell to a next-stage circuit cell and an allowable longest wiring resistance RtL drivable by the target circuit cell are compared. When Rpath is less than or equal to RtL (S4: YES), the sum Rtotal of resistances of wiring loads in a net and RtL are compared. If Rtotal is less than or equal to RtL (S5: YES), then the next-stage circuit cell is judged to be drivable within a predetermined waveform rounding limit value. When Rtotal is greater than RtL (S5: NO), an effective resistance Rw of each wiring load and an allowable longest wiring effective resistance RwL are compared.