Patents by Inventor Miyako Uchida

Miyako Uchida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Memory access processing method and information processing device
    Patent number: 9507724
    Abstract: A memory access processing method includes storing, in a cache memory, a plurality of pages stored in a main memory; storing the plurality of pages in a buffer memory, each of the plurality of pages being associated with an identifier indicating whether the each of the plurality of pages being a zero page to be zero-cleared; allocating a page to be set to a zero page, when a page fault occurs during execution of an access to the cache memory and execution of a process is stopped; updating an identifier corresponding to the allocated page to an identifier indicating the allocated page being the zero page; resuming the execution of the process; controlling an access to the cache memory, based on the identifier for each of the plurality of pages; and executing initialization of a page corresponding to the allocated page and is included in the main memory.
    Type: Grant
    Filed: August 3, 2015
    Date of Patent: November 29, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Hiroyuki Kamezawa, Yasuo Ueda, Tsutomu Itoh, Hideo Shitaya, Yasunori Goto, Miyako Uchida, Ken Ichikawa, Hidetoshi Seto
  • MEMORY ACCESS PROCESSING METHOD AND INFORMATION PROCESSING DEVICE
    Publication number: 20160062902
    Abstract: A memory access processing method includes storing, in a cache memory, a plurality of pages stored in a main memory; storing the plurality of pages in a buffer memory, each of the plurality of pages being associated with an identifier indicating whether the each of the plurality of pages being a zero page to be zero-cleared; allocating a page to be set to a zero page, when a page fault occurs during execution of an access to the cache memory and execution of a process is stopped; updating an identifier corresponding to the allocated page to an identifier indicating the allocated page being the zero page; resuming the execution of the process; controlling an access to the cache memory, based on the identifier for each of the plurality of pages; and executing initialization of a page corresponding to the allocated page and is included in the main memory.
    Type: Application
    Filed: August 3, 2015
    Publication date: March 3, 2016
    Inventors: Hiroyuki KAMEZAWA, Yasuo UEDA, TSUTOMU ITOH, Hideo Shitaya, Yasunori Goto, Miyako Uchida, Ken Ichikawa, Hidetoshi Seto