Abstract: Memory cell columns formed by connecting a plurality of memory cells in a memory cell array block A1 by a predetermined number a1, a2, b1, b2 are arranged in the order of "a1, b1, b2 and a2"; a row decoder D1 for selecting a word line for the memory cell columns a1 and a2 and a row decoder D2 for selecting a word line for the memory cell columns b1 and b2 are arranged on both sides of the memory cell array block A1; a word line is connected via contact areas C1, C3 and C2; a word line is separated by areas H1 and H2 between memory cells respectively between the memory cell columns a1 and b1 and the memory cell columns b2 and a2; digital lines are connected to each other between the memory cell columns a1 and b1 and the memory cell columns b2 and a2; and one sense amplifier circuit is arranged every pitch between two cells.