Abstract: A communications node includes a first transmitting circuit configured to transmit to plural communications nodes, a confirmation signal for confirming whether response is possible; a receiving circuit configured to receive from first communications nodes capable of responding among the plural communications nodes, a response signal for the transmitted confirmation signal; a selecting circuit configured to select from among the first communications nodes and based on reception strength of the received response signal, a second communications node to which execution of data processing is requested by the communications node; a strength calculating circuit configured to calculate based on the reception strength of the response signal from the selected second communications node, a transmission strength to the second communications node; and a second transmitting circuit configured to transmit to the second communications node and based on the calculated transmission strength, a request signal requesting executi

Abstract: A communications node includes a first transmitting circuit configured to transmit to plural communications nodes, a confirmation signal for confirming whether response is possible; a receiving circuit configured to receive from first communications nodes capable of responding among the plural communications nodes, a response signal for the transmitted confirmation signal; a selecting circuit configured to select from among the first communications nodes and based on reception strength of the received response signal, a second communications node to which execution of data processing is requested by the communications node; a strength calculating circuit configured to calculate based on the reception strength of the response signal from the selected second communications node, a transmission strength to the second communications node; and a second transmitting circuit configured to transmit to the second communications node and based on the calculated transmission strength, a request signal requesting executi

Abstract: An RC generating unit generates a first ranging code by performing a logical operation to first seed data, repeats a process for generating a second ranging code by performing the logical operation to second seed data generated when generating the first ranging code until generation of a Nth ranging code, stores the 1st through Nth seed data corresponding to the 1st through Nth ranging codes in the memory. And the RC generating unit generates a transmission ranging code, in response to a reception of specification data of a transmission ranging code transmitted from a base station, by performing the logical operation to the seed data corresponding to the specification data.

Abstract: An RC generating unit generates a first ranging code by performing a logical operation to first seed data, repeats a process for generating a second ranging code by performing the logical operation to second seed data generated when generating the first ranging code until generation of a Nth ranging code, stores the 1st through Nth seed data corresponding to the 1st through Nth ranging codes in the memory. And the RC generating unit generates a transmission ranging code, in response to a reception of specification data of a transmission ranging code transmitted from a base station, by performing the logical operation to the seed data corresponding to the specification data.

Abstract: A radio communications device includes a first error detection part configured to perform error detection on a header included in a packet; a determination part configured to determine whether there is consistency with respect to the length of the packet based on the header in response to the first error detection part detecting no error in the header; a decryption part configured to decrypt the packet in response to the determination part determining that there is consistency with respect to the length of the packet; and a second error detection part configured to perform error detection on the packet in response to the determination part determining that there is consistency with respect to the length of the packet, wherein the decryption part is configured to start to decrypt the packet before completion of the error detection by the second error detection part.

Abstract: A semiconductor device includes a plurality of memories, a sequencer which outputs configuration information, and a memory reconfiguring circuit which reconfigures the memory area in accordance with the configuration information supplied from the sequencer. Since the memory reconfiguring circuit dynamically changes the allocation of the memories, it is possible to reconfigure the memory configuration and freely change the memory size in accordance with the purpose of use.

Abstract: A reconfigurable circuit and control method therefor, capable of enhancing efficiency of implementation of a pipeline process in processing elements and improve processing performance. Processing elements are reconfigured to form a circuit based on configuration information and execute a prescribed process. Memory units store configuration information for the processing elements. A memory switching unit switches the plurality of memory units to store therein the configuration information on the stages of a pipeline process to be performed by the processing elements. A configuration information output unit switches the memory units to output therefrom the configuration information to the plurality of processing elements.

Abstract: An operation apparatus includes a sequencer controlling states of a plurality of operation devices and a configuration memory storing therein configuration information as setting information for each state in the operation device. In the operation apparatus, a path which requires a data buffer and another path which requires no such a data buffer are provided for inputting data to the operation device, a data buffer control part is provided for controlling selection from these two paths and operation of the data buffer, and contents of path selection and operation control of the data buffer carried out by the data buffer control part are set according to the configuration information.

Abstract: A reconfigurable operation apparatus consists of a plurality of operation units capable of reconfiguring themselves by using a piece of given first configuration data and of operating simultaneously with one another; RAMs; diverse processor elements required for constituting an operation apparatus; an inter-resource network interconnecting the operation units, the RAMs and the diverse processor elements, performing data transfers between resources connected thereto in a uniform transfer time independent of positions and kinds of the resources, and being reconfigurable by using a given second configuration data; and a configuration memory storing the first and the second configuration data. Configuration data is loaded from an external storage apparatus onto the configuration memory, and the first and the second configuration data are supplied to the reconfigurable processor resources in appropriate sequence and timing based on data available from a plurality of operation units.

Abstract: The present invention provides a reconfigurable processing apparatus enabling clusters to utilize a shared functional unit by using data and a validity signal received from the clusters by way of a network therebetween. In the reconfigurable processing apparatus comprising one or more clusters which are reconfigured based on configuration information, the shared functional unit accepts an input data and an input valid signal from the clusters, the input valid signal starts up the shared functional unit so as to operate the input data received with the input valid signal and output, to the cluster, an output data as the operation result and an output valid signal for notifying of the cluster as an output destination of the aforementioned output data.

Abstract: An operation apparatus includes a plurality of operation device units; a configuration memory storing setting information provided for each predetermined state of the plurality of operation device units; and a sequencer controlling the plurality of operation device units by outputting transition destination addresses designating relevant information from configuration information comprising the setting information provided for each state of the operation device units stored in the configuration memory, wherein the sequencer carries out operation based on task information previously loaded and a change-over condition signal output from the plurality of operation device units, and generates the transition destination address to output to the configuration memory.

Abstract: An integrated circuit includes a processor. An arithmetic logic circuit group includes a plurality of operation units and a connection channel connecting the operation units in a reconfigurable manner. Parameter-based dedicated hardware can change a process specification thereof by parameter setting. An intermodule interface connects the processor, the arithmetic logic circuit group, and the parameter-based hardware to each other.

Abstract: A packet processing device for processing data conveyed by at least one data block including a plurality of packets including a control packet having control data, includes: a packet processor for receiving and storing the data block; and a controller for processing data in each data block stored in the packet processor, wherein the controller processes each of the packets in a data block successively received by the packet processor packet by packet until the controller finds a control packet among the processed packets in the data block, and upon finding of the control packet in the data block, the controller collectively processes remainder of the data in the data block.

Abstract: An arithmetic unit capable of reconfiguring circuitry in accordance with configuration data supplied includes a data processing unit performing a processing using input data; an output data maintenance unit maintaining the result of the processing to output it as an output data; and an output valid signal control unit outputting an output valid signal indicating whether or not the output data is valid, in which an output timing of a valid data to outside the arithmetic unit can be controlled optionally by controlling the output timing of the output valid signal.

Abstract: A radio communications device includes a first error detection part configured to perform error detection on a header included in a packet; a determination part configured to determine whether there is consistency with respect to the length of the packet based on the header in response to the first error detection part detecting no error in the header; a decryption part configured to decrypt the packet in response to the determination part determining that there is consistency with respect to the length of the packet; and a second error detection part configured to perform error detection on the packet in response to the determination part determining that there is consistency with respect to the length of the packet, wherein the decryption part is configured to start to decrypt the packet before completion of the error detection by the second error detection part.

Abstract: A signal transmission system is constructed to transmit data over a signal transmission line without requiring precharging the signal transmission line for every bit, by eliminating the intersymbol interference component introduced by preceding data. The signal transmission line has a plurality of switchable signal transmission lines organized in a branching structure or a hierarchical structure, at least one target unit from which to read data is connected to each of the plurality of signal transmission lines, and a readout circuit including a circuit for eliminating the intersymbol interference component is connected to the signal transmission line, wherein the intersymbol interference component elimination circuit reduces noise introduced when the signal transmission line is switched between the plurality of signal transmission lines, and thereby provides a smooth intersymbol interference component elimination operation when the signal transmission line is switched.

Abstract: A network structure configures a blocking network having constraint against such a combination of said network input terminal and network output terminal as to make it unfeasible to further connect, when connecting first network input terminals to first network output terminals, second network input terminals to any one of the second network output terminals, and operation elements and the network output terminals are connected so as to minimize a constraint strength between the plurality of network output terminals inputting to the same operation element with respect to the constraint strength defined as the number of network input terminals contained in tuples of network input terminals to which the two network output terminals in the network output terminals can not be simultaneously connected.

Abstract: An arithmetic unit capable of reconfiguring circuitry in accordance with configuration data supplied includes a data processing unit performing a processing using input data; an output data maintenance unit maintaining the result of the processing to output it as an output data; and an output valid signal control unit outputting an output valid signal indicating whether or not the output data is valid, in which an output timing of a valid data to outside the arithmetic unit can be controlled optionally by controlling the output timing of the output valid signal.

Abstract: A reconfigurable circuit and control method therefor, capable of enhancing efficiency of implementation of a pipeline process in processing elements and improve processing performance. Processing elements are reconfigured to form a circuit based on configuration information and execute a prescribed process. Memory units store configuration information for the processing elements. A memory switching unit switches the plurality of memory units to store therein the configuration information on the stages of a pipeline process to be performed by the processing elements. A configuration information output unit switches the memory units to output therefrom the configuration information to the plurality of processing elements.

Abstract: A signal transmission system is constructed to transmit data over a signal transmission line without requiring precharging the signal transmission line for every bit, by eliminating the intersymbol interference component introduced by preceding data. The signal transmission line has a plurality of switchable signal transmission lines organized in a branching structure or a hierarchical structure, at least one target unit from which to read data is connected to each of the plurality of signal transmission lines, and a readout circuit including a circuit for eliminating the intersymbol interference component is connected to the signal transmission line, wherein the intersymbol interference component elimination circuit reduces noise introduced when the signal transmission line is switched between the plurality of signal transmission lines, and thereby provides a smooth intersymbol interference component elimination operation when the signal transmission line is switched.