Patents by Inventor Miyuki Akazawa

Miyuki Akazawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8069560
    Abstract: A manufacturing method of a multilayer wiring board that includes a core board, a wiring layer, and an electrically insulating layer that are stacked on the core board. The manufacturing method forms a plurality of through holes in a core member, a thermal expansion coefficient of the core board being between 2 to 20 ppm, and the core member selected from silicon, ceramics, glass, a glass-epoxy composite, and metal. The through holes are made conductive by a conductive material, to electrically connect between the front and the back of the core board. A wiring layer and an electrically insulating layer are stacked on one surface of the core board to form a multilayer wiring layer. A capacitor is formed on the other surface of the core board.
    Type: Grant
    Filed: February 18, 2010
    Date of Patent: December 6, 2011
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventors: Toshiaki Mori, Kazunori Nakamura, Satoru Kuramochi, Miyuki Akazawa, Koichi Nakayama
  • Publication number: 20110035939
    Abstract: In a multilayer wiring board comprising a core board, and a wiring layer and an electrically insulating layer that are stacked on one surface of said core board, a thermal expansion coefficient of said core board in XY directions falls within a range of 2 to 20 ppm, a core member for said core board is a core member selected from silicon, ceramics, glass, a glass-epoxy composite, and metal, said core board is provided with a plurality of through holes that are made conductive between the front and the back by a conductive material, and a capacitor is provided on one surface of said core board, wherein said capacitor comprises an upper electrode being the conductive material in said through hole, and a lower electrode disposed so as to confront said upper electrode via a dielectric layer.
    Type: Application
    Filed: February 18, 2010
    Publication date: February 17, 2011
    Applicant: DAI NIPPON PRINTING CO., LTD.
    Inventors: Toshiaki MORI, Kazunori Nakamura, Satoru Kuramochi, Miyuki Akazawa, Koichi Nakayama
  • Patent number: 7690109
    Abstract: In a multilayer wiring board comprising a core board, and a wiring layer and an electrically insulating layer that are stacked on one surface of said core board, a thermal expansion coefficient of said core board in XY directions falls within a range of 2 to 20 ppm, a core member for said core board is a core member selected from silicon, ceramics, glass, a glass-epoxy composite, and metal, said core board is provided with a plurality of through holes that are made conductive between the front and the back by a conductive material, and a capacitor is provided on one surface of said core board, wherein said capacitor comprises an upper electrode being the conductive material in said through hole, and a lower electrode disposed so as to confront said upper electrode via a dielectric layer.
    Type: Grant
    Filed: April 26, 2006
    Date of Patent: April 6, 2010
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventors: Toshiaki Mori, Kazunori Nakamura, Satoru Kuramochi, Miyuki Akazawa, Koichi Nakayama
  • Publication number: 20060185141
    Abstract: In a multilayer wiring board comprising a core board, and a wiring layer and an electrically insulating layer that are stacked on one surface of said core board, a thermal expansion coefficient of said core board in XY directions falls within a range of 2 to 20 ppm, a core member for said core board is a core member selected from silicon, ceramics, glass, a glass-epoxy composite, and metal, said core board is provided with a plurality of through holes that are made conductive between the front and the back by a conductive material, and a capacitor is provided on one surface of said core board, wherein said capacitor comprises an upper electrode being the conductive material in said through hole, and a lower electrode disposed so as to confront said upper electrode via a dielectric layer.
    Type: Application
    Filed: April 26, 2006
    Publication date: August 24, 2006
    Applicant: DAI NIPPON PRINTING CO., LTD.
    Inventors: Toshiaki Mori, Kazunori Nakamura, Satoru Kuramochi, Miyuki Akazawa, Koichi Nakayama
  • Patent number: 7091589
    Abstract: In a multilayer wiring board comprising a core board, and a wiring layer and an electrically insulating layer that are stacked on one surface of said core board, a thermal expansion coefficient of said core board in XY directions falls within a range of 2 to 20 ppm, a core member for said core board is a core member selected from silicon, ceramics, glass, a glass-epoxy composite, and metal, said core board is provided with a plurality of through holes that are made conductive between the front and the back by a conductive material, and a capacitor is provided on one surface of said core board, wherein said capacitor comprises an upper electrode being the conductive material in said through hole, and a lower electrode disposed so as to confront said upper electrode via a dielectric layer.
    Type: Grant
    Filed: December 10, 2003
    Date of Patent: August 15, 2006
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventors: Toshiaki Mori, Kazunori Nakamura, Satoru Kuramochi, Miyuki Akazawa, Koichi Nakayama
  • Publication number: 20050012217
    Abstract: In a multilayer wiring board comprising a core board, and a wiring layer and an electrically insulating layer that are stacked on one surface of said core board, a thermal expansion coefficient of said core board in XY directions falls within a range of 2 to 20 ppm, a core member for said core board is a core member selected from silicon, ceramics, glass, a glass-epoxy composite, and metal, said core board is provided with a plurality of through holes that are made conductive between the front and the back by a conductive material, and a capacitor is provided on one surface of said core board, wherein said capacitor comprises an upper electrode being the conductive material in said through hole, and a lower electrode disposed so as to confront said upper electrode via a dielectric layer.
    Type: Application
    Filed: December 10, 2003
    Publication date: January 20, 2005
    Inventors: Toshiaki Mori, Kazunori Nakamura, Satoru Kuramochi, Miyuki Akazawa, Koichi Nakayama