Patents by Inventor Miyuki Ikeda

Miyuki Ikeda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5225714
    Abstract: Electric charges are stored on a capacitor and then the charges are discharged so that a sawtooth wave for use in a convergence correction circuit for a display or the like is generated. When the sawtooth wave is used for a multi-scan display, the charge period is varied according as the scanning frequency varies, and as a result, a phase error is produced in the parabolic wave obtained by squaring the sawtooth wave. To eliminate the phase error, it is adapted such that the discharging current from the capacitor is passed through a coil and, in addition, the period as the reciprocal of the resonant frequency of the resonance circuit formed of the coil and the capacitor is set to be virtually double the discharge period.
    Type: Grant
    Filed: December 10, 1990
    Date of Patent: July 6, 1993
    Assignee: Hitachi, Ltd.
    Inventors: Toshiyuki Kimoto, Miyuki Ikeda
  • Patent number: 5194783
    Abstract: A digital convergence correction circuit for a CRT display unit deals with the problem of an excessive calculation time of the microprocessor expended for the vertical interpolation by using at least two pieces of ROM (read only memory) devices connected together. The circuit deals with the problem of a step variation of brightness by employment of a novel slope interpolation means which implements interpolation based on a continuous waveform of the first-order differential coefficient at the lattice points of the display screen and a curve interpolation means which forms a more superior convergence system. The circuit uses a blanking means to prevent abnormal states from appearing on the display screen during the transfer period of the digital convergence correction data of a new format at the switching of the scanning format for a video signal to be displayed.
    Type: Grant
    Filed: June 4, 1992
    Date of Patent: March 16, 1993
    Assignee: Hitachi, Ltd.
    Inventors: Masanori Ogino, Takeo Yamada, Miyuki Ikeda, Takashi Azuma, Satoshi Ootomo
  • Patent number: 5189347
    Abstract: A video output circuit for driving a CRT of a grid-cathode differential drive type is disclosed, in which a collector potential of an output transistor in a horizontal blanking interval is detected by a diode arrangement; the potential thus detected is smoothed by a smoothing filtering arrangement output current of the output transistor is controlled by an output obtained by the smoothing filtering arrangement; and negative feedback control is effected so that the collector potential of the output transistor is made constant. In this way, a bias adjusting power supply, which was required heretofore, is made unnecessary.
    Type: Grant
    Filed: December 19, 1991
    Date of Patent: February 23, 1993
    Assignee: Hitachi, Ltd.
    Inventors: Masanori Ogino, Takeo Yamada, Miyuki Ikeda, Tsueno Fujikura, Takahiko Fujiwara
  • Patent number: 5070281
    Abstract: A CRT display including a horizontal deflection circuit. The horizontal deflection coil supplied with a horizontal deflection signal, with inductance L, has an energy-dissipating coil resistance connected in series and hence a second-order distortion expanding the left-hand side of the picture screen of the display and contracting the right-hand side thereof is produced. In the preset invention, to correct for the second-order distortion, the current flowing through the deflection coil means is detected, the deflection distortion component is extracted from the current, and a deflection distortion correcting current corresponding to the deflection distortion is supplied to an auxiliary coil for correcting the horizontal deflection of the electron beam.
    Type: Grant
    Filed: May 21, 1990
    Date of Patent: December 3, 1991
    Assignee: Hitachi, Ltd.
    Inventors: Masanori Ogino, Takeo Yamada, Miyuki Ikeda
  • Patent number: 5053724
    Abstract: In a high prrecision PLL circuit arrangement, a phase detecting circuit produces a detecting signal which is directly proportional to a phase difference between a horizontal synchronizing signal and a voltage-controlled oscillating signal. A loop filter circuit produces a delay signal for delaying a frequency control at a predetermined time constant in response to the detecting signal derived from the phase detecting circuit. A voltage-controlled oscillating circuit produces an oscillating signal having a frequency directly proportional to a voltage of the delay signal from the loop filter circuit. A non-linear circuit includes a non-linear element for changing at least one of an AC gain and a DC gain of the loop filter circuit, and prevents an erroneous capture phenomenon of the PLL circuit arrangement in response to the detecting signal from the phase detecting circuit.
    Type: Grant
    Filed: May 29, 1990
    Date of Patent: October 1, 1991
    Assignee: Hitachi, Ltd.
    Inventors: Masanori Ogino, Takeo Yamada, Miyuki Ikeda
  • Patent number: 5039923
    Abstract: A focus adjusting device for projection display, comprising at least one set of 4-pole magnetic field generating means, and adjustment means for adjusting the magnetic field strength of the 4-pole magnetic field generating means so as to eliminate astigmatism caused by fabrication error and attachment error of an electron gun and a focus coil.
    Type: Grant
    Filed: October 17, 1989
    Date of Patent: August 13, 1991
    Assignee: Hitachi, Ltd.
    Inventors: Masanori Ogino, Takeo Yamada, Miyuki Ikeda, Ichiro Niitsu
  • Patent number: 5010280
    Abstract: A vertical deflection circuit for a CRT display device comprises a first negative feedback circuit for detecting a vertical deflection current flowing through a vertical deflection coil feeding it back to a ramp wave generator to thereby stabilize a vertical size of the display image on the CRT screen, second negative feedback circuit connected between the deflection coil to an input of the output circuit for detecting a mean vertical deflection current which is fedback to an output circuit to thereby stabilize a vertical position of the display image on the CRT screen and a controlling circuit for controlling feedback amount of the first and second negative feedback circuits to thereby regulate a vertical size and a vertical position of the display image on the CRT screen variably.
    Type: Grant
    Filed: April 26, 1990
    Date of Patent: April 23, 1991
    Assignee: Hitachi, Ltd.
    Inventors: Masanori Ogino, Takeo Yamada, Miyuki Ikeda
  • Patent number: 4980614
    Abstract: A convergence correction circuit according to the present invention has a phased locked loop including a programmable counter. The programmable counter has programmable count start and end points. The output of the programmable counter is supplied to a memory storing convergence distortion correcting data therein. As the horizontal screen size is increased, a value closer to the lower limit 0 of the start point as compared with that taken when the horizontal size is small is set as the count start point of the programmable counter, and a value closer to the upper limit (2.sup.7 -1) of the end point as compared with that taken when the horizontal size is small is set as the count end point. In accordance with the horizontal screen size, the count start and end points of the programmable counter are changed. Correct convergence correction is performed even if the horizontal screen size is changed.
    Type: Grant
    Filed: May 16, 1988
    Date of Patent: December 25, 1990
    Assignee: Hitachi, Ltd.
    Inventors: Takeo Yamada, Miyuki Ikeda, Toshiyuki Kimoto, Masanori Ogino, Tsuneo Fujikura, Yoshihiro Arakawa
  • Patent number: 4961030
    Abstract: The present invention relates to a miss convergence compensating circuit of a projection type display. The projection type display is provided with three projection tubes for red, green and blue colors and a color image is obtained by combining three colors from three projection tubes on a screen. When such projection tubes are arranged slant to the screen, miss convergence is generated on the screen. A convergence yoke for auxiliary deflection of electron beam is generally provided in order to compensate for such miss convergence, but this convergence yoke has the deflection sensitivity which is worse than that of deflection yoke. Therefore, the present invention contributes to compensate for miss convergence using the deflection yokes. For this purpose, at least two deflection coils are provided with a transformer coupling which allow the compensating currents corresponding to the miss convergence compensating signals to flow.
    Type: Grant
    Filed: May 18, 1989
    Date of Patent: October 2, 1990
    Assignee: Hitachi, Ltd.
    Inventors: Masanori Ogino, Takeo Yamada, Miyuki Ikeda, Toshiyuki Kimoto
  • Patent number: 4952850
    Abstract: A horizontal deflection circuit for a multiple scan display, capable of controlling the horizontal deflection voltage for a plurality of horizontal scanning frequencies. The output power of the amplifier is controlled on the basis of the result of detection of the data of horizontal size of the image plane so that the horizontal size of the image plane is adjusted to a predetermined size. The data of horizontal size of the image plane is obtained through the detection of the amplitude of a flyback pulse signal. The amplitude of a sawtooth signal for horizontal scanning is controlled according to the deviation of the detected amplitude of the flyback pulse signal from a predetermined value. The horizontal deflection circuit is very simple in construction and is capable of carrying out continuous horizontal deflection according to the horizontal scanning frequency varying in a plurality of levels.
    Type: Grant
    Filed: July 12, 1989
    Date of Patent: August 28, 1990
    Assignee: Hitachi, Ltd.
    Inventors: Masanori Ogino, Takeo Yamada, Miyuki Ikeda
  • Patent number: 4918359
    Abstract: A vertical deflection circuit used in a cathode ray tube display device for shortening a vertical blanking period is disclosed which includes back-flow blocking diode means for preventing an oscillating current from flowing backward to a vertical push-pull output amplifier circuit in the vertical blanking period, resonating capacitor means, and electrostatic energy supplying means for energizing a fly-back pulse. The resonating capacitor means is provided to generate resonance due to the capacitance of the capacitor means and the inductance of a vertical deflection coil, on the basis of the electro-magnetic energy of the vertical deflection coil at a time immediately before a retrace line starts from the bottom of display screen, thereby producing a fly-back pulse. The back-flow blocking diode means prevents the fly-back pulse from flowing backward to the vertical output circuit, that is, prevents the fly-back pulse from de-energizing the output of the vertical output circuit.
    Type: Grant
    Filed: April 10, 1989
    Date of Patent: April 17, 1990
    Assignee: Hitachi, Ltd.
    Inventors: Masanori Ogino, Takeo Yamada, Miyuki Ikeda
  • Patent number: 4897581
    Abstract: A horizontal deflection circuit which including a horizontal output transistor; a damper diode connected in parallel with the horizontal output transistor; a resonant capacitor connected in parallel with the damper diode; a horizontal deflection coil connected in parallel with the horizontal output transistor; and a series resonant circuit connected in parallel with the resonant capacitor. The series resonant circuit is constituted by a series connection of a capacitor and an inductor to perform composite resonance in cooperation with the resonant capacitor. The capacitor and the inductor of the series resonant circuit are designed to have a tertiary resonant frequency. The composite resonance by means of the series resonant circuit and the resonant capacitor enables the top of the flyback pulse to be flattened, so that the waveform of the flyback pulse becomes near the form of rectangular wave.
    Type: Grant
    Filed: January 13, 1989
    Date of Patent: January 30, 1990
    Assignee: Hitachi, Ltd.
    Inventors: Masanori Oguino, Takeo Yamada, Miyuki Ikeda
  • Patent number: 4891608
    Abstract: A horizontal oscillation circuit which prevents damage of horizontal output transistors due to the rapid increase of horizontal deflection current at varying states of horizontal scan frequency or at the turning-on state of the power source. The horizontal oscillation circuit is provided with a speed up circuit which rapidly increases the control voltage supplied to a control voltage terminal of a voltage controlled oscillator. This provides increased speed of the oscillation frequency of the voltage controlled oscillator which does not slow in comparison to increasing speed of power source voltage. Consequently, the horizontal deflection current remains nearly constant, even at varying states of the horizontal scan frequency of the turning-on state of the power source, and damage to horizontal output transistors is avoided.
    Type: Grant
    Filed: July 13, 1988
    Date of Patent: January 2, 1990
    Assignee: Hitachi, Ltd.
    Inventor: Miyuki Ikeda