Patents by Inventor Miyuki Nagata

Miyuki Nagata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5452428
    Abstract: An information processing apparatus executes a machine language instruction according to a microprogram controlling method. The apparatus comprises an instruction decoder for decoding the machine language instruction; an operand controller for receiving from the instruction decoder, information about operands that are necessary in executing the machine language instruction, and fetching and holding the operands according to the information; and an instruction executing device generating operand requests to the operand controller, obtaining the operands, and executing the machine language instruction under the control of a microprogram. Thus, the apparatus can execute a plurality of machine language instructions that respectively prescribe the same operation to be carried out on the different kinds of operands, under the control of a single microprogram irrespective of the differences of the kinds of the operands.
    Type: Grant
    Filed: January 13, 1995
    Date of Patent: September 19, 1995
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Miyuki Nagata, Tohru Utsumi
  • Patent number: 5117487
    Abstract: In a microprocessor, a microinstruction is used to control the microprocessor.
    Type: Grant
    Filed: August 25, 1989
    Date of Patent: May 26, 1992
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Miyuki Nagata
  • Patent number: 5077659
    Abstract: A data processor having an inner instruction register, a microinstruction register, and microinstruction decoder for decoding the microinstruction stored in the microinstruction register, and a data expansion section for expanding data bits stored in source and destination registers among general purpose registers when designated by an inner instruction in which the bit lengths of data to be processed can be designated by an inner instruction, a microinstruction for performing the operation of data having same contents but different bit lengths can be made common, thereby reducing the number of steps of the microprograms.
    Type: Grant
    Filed: December 20, 1990
    Date of Patent: December 31, 1991
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Miyuki Nagata
  • Patent number: 4839839
    Abstract: Where an N-bit input data is rotated together with a carry bit by an N-bit or more rotate count, the actual rotate count is obtained as a remainder or modulo of x/N+1 (x: rotate count; N: data bit length). The above remainder will not be obtained by simply masking shift signals. Therefore, the remainder is calculated at high speed through hardware including a subtrahend calculator section for calculating (N+1) (i) (i=0, 1, 2, . . . ) and a subtracter section for calculating {x-(N+1) (i)} to obtain a modulo or a remainder representative of an actual rotate count.
    Type: Grant
    Filed: September 28, 1987
    Date of Patent: June 13, 1989
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeji Tokumaru, Miyuki Nagata