Abstract: An interrupt coupling scheme for a multiprocessor data processing network capable of providing the current status of all interrupts to all processors in the network employs an associated interrupt latch for each processor, to which the lines of the system data bus are bidirectionally coupled, and an address decoder that is coupled to the system address bus. When a processor wishes to interrupt another processor it drives the data bus so as to set the corresponding latch bit in the addressed processor's interrupt status latch, thereby presenting to the addressed processor an interrupt request signal.The contents of the interrupt request latch are selectively masked by the destination processor and then encoded into an interrupt vector to which the destination processor responds during its task assignment operations.

Abstract: A bus arbitration arrangement for resolving competing requests for access to a bus is associated with local signal control lines, that are coupled to its associated "master" (i.e. user of the bus), and control lines of the bus common to all other units. These local signal control lines include a set of identification lines defining the address (and priority rank) of the associated master, a request line through which the master requests access to the bus, a grant line through which a master is informed that it has control of the bus, and a release line through which the master informs the bus exchange control circuit that it is releasing its control of the bus.