Abstract: In a nonvolatile semiconductor memory device, a wiring layer is connected between a power source and a memory cell. Resistance of the wiring layer is larger than the on-resistance of a load transistor, so that the load transistor substantially determines the load characteristic. Therefore, the load characteristic curve is more gentle in inclination and more rectilinear in shape. This makes the data writing operation stable against a variance in the channel lengths of manufactured transistors forming the memory cells.

Abstract: A semiconductor memory device includes word lines selectively driven by a signal from a row decoder, memory cells connected to word lines, first and second data lines, a bit line connected to receive data from the memory cell and to supply received data to the first data lines, dummy cells connected to word lines, first and second dummy data lines, a dummy bit lines connected to receive data from the dummy memory cell and to supply received data to the first dummy data line, a data sensing circuit for generating an output signal corresponding to a potential difference between the second data line and second dummy data line, a first MOS transistor connected between the first and second data lines, a first load circuit for charging the second data line, a second MOS transistor connected between the first and second dummy data lines, and a second load circuit for charging the second dummy data lines.

Abstract: An atomizer for forming a thin film comprising an atomizing box, a guide tube having an open end of small diameter and an other open end of large diameter, a nozzle having an ejection outlet disposed in the atomizing box, an atomizing solution reservoir defined in the atomizing box adjacent to the open end of large diameter of the guide tube, and a fluid return passage defined around the circumference of the guide tube for returning the atomized solution from the atomizing solution reservoir to the one open end thereof. The atomizing box can contain a plurality of guide tubes each provided with a nozzle. The guide tube can also have a plurality of nozzles positioned therein.

Abstract: There is disclosed an atomized thin film forming apparatus for forming a thin film by spouting an atomized source solution toward a heated substrate. A pair of inner wall surfaces defined at the upper portion of a film forming nozzle and disposed opposite to each other with respect to the longitudinal direction of a film forming chamber are restricted so as to gradually narrow in the interval therebetween toward a spouting opening in a smooth curve. Hence, it is possible to prevent a mist of the source solution atomized by the atomizer from being locally stagnant in the film forming nozzle and prevent a precipitate of the atomized source solution from growing. Consequently, the flow of the mist of the source solution is not hindered by the precipitation of the atomized source solution so that the thin film is formed over the surface of the substrate at a high uniformity for a long period of time.

Abstract: A thin film forming apparatus which forms a thin film over a surface of a subtrate by spraying a mist of a source solution produced by atomization over the surface of the substrate heated to a given temperature. The film forming apparatus is provided with a pair of guide members for supporting and guiding the substrate at opposite sides of the same. The distance between the opposite inner surfaces of the guide members can be changed according to the width of the substrate to be supported and guided by the pair of guide members. The distance between the respective lower portions of the opposite inner surfaces of the pair of guide members is greater than the distance between the upper portions of the opposite inner surfaces of the same, so that the distribution of the flow rate per unit flow passage area of the mist of the source solution is uniform with respect to the width of the substrate and enables a thin film of a uniform thickness to be formed over the entire surface of the substrate.

Abstract: A thin film forming apparatus which forms a thin film over the film forming surface of a substrate by spraying a mist of a source solution produced by atomization over the film forming surface of the substrate heated to a given temperature. The substrate conveying direction is reversible, or a nozzle for spouting the mist into a film forming chamber and an exhaust duct are connected removably to a hearth forming the bottom wall of the film forming chamber and can be switched with one another. The film forming apparatus is capable of forming thin films of different laminate constructions.

Abstract: This invention relates to a method for forming a transparent conductive metal oxide film having good characteristic properties. The method comprises feeding an atomized or gasified starting material onto a substrate to form a metal oxide film on the substrate, wherein the substrate is heated to form a first metal oxide film having a good degree of orientation of crystals and a second film formation step wherein a second metal oxide film is formed on the first metal oxide film under higher substrate temperature conditions than those in the first film formation step to form a second metal oxide film having a degree of orientation of crystals in conformity with that of the first metal oxide film.

Abstract: In a nonvolatile semiconductor memory device, a wiring layer is connected between a power source and a memory cell. Resistance of the wiring layer is larger than the on-resistance of a load transistor, so that the load transistor substantially determines the load characteristic. Therefore, the load characteristic curve is more gentle in inclination and more rectilinear in shape. This makes the data writing operation stable against a variance in the channel lengths of manufactured transistors forming the memory cells.

Abstract: A semiconductor memory device in which data can be read out in response to an address signal comprises power source lines, a plurality of row and column conductive lines, a memory cell array including nonvolatile memory cells arranged in a matrix form of rows and columns and respectively connected to the plurality of row and column lines and the power source lines, a first selector circuit for generating a signal for selecting the row conductive lines in response to an address signal, a dummy row line, and a dummy memory cells each having a source, a drain and a control gate connected to the dummy row line.

Abstract: A semiconductor integrated circuit includes a CMOS circuit operated on a voltage of a first voltage level to set an output node thereof to a voltage of the first voltage level or a reference voltage; an output circuit for controlling supply of a voltage of a second voltage level which is higher than the first voltage level to a signal output node; and an isolation MOS transistor having a current path connected between the output node of the CMOS circuit and the signal output node and a gate connected to receive a control signal. The output node of the CMOS circuit is set to the reference voltage with the conduction resistance of the isolation MOS transistor kept high after the lapse of period in which the voltage of the second voltage level is kept supplied to the signal output node. After this, the conduction resistance of the isolation MOS transistor is reduced in response to the control signal.

Abstract: A semiconductor integrated circuit includes an output circuit and a control circuit for controlling the output circuit. The control circuit controls the output circuit so as to charge or discharge a preset node in the output circuit at a rate different from an ordinary charging or discharging rate for a preset period of time after a control signal has been changed in level.

Abstract: A semiconductor memory device has a redundancy circuit for compensating a defective bit when it occurs in the main memory cells. The redundancy circuit includes spare memory cells, a spare row decoder for selecting the spare memory cells, a first circuit section for inhibiting the use of the main row decoder when the spare row decoder is used, and a second circuit section for selecting the spare row decoder when an address specifying the main row line connected to the defective memory cell is denoted.