Abstract: Gate insulating film, gate electrode made up of lower and upper gate electrodes, and on-gate passivation film are formed in this order on an Si substrate. Then, a sidewall is formed as a stack of an oxynitride sidewall having an L-shaped cross section and a nitride sidewall, so as to surround the gate electrode and on-gate passivation film. Alternatively, only the lower edge of an L-oxide sidewall may be changed into an oxynitride region. Or an oxide or stacked sidewall and a nitride sidewall, covering the oxide or stacked sidewall, may be formed instead of the oxynitride sidewall. In any of these embodiments, the lower edge of the sidewall is not removed during a wet etching process.

Abstract: A gate insulating film, a gate electrode, a gate-top protection film, LDD layers and nitride film sidewalls are formed on a semiconductor substrate. Source/drain regions are formed in the semiconductor substrate. After deposition of an interlayer insulating film on the resultant substrate, a hole is formed through the interlayer insulating film and the gate-top protection film to reach the gate electrode, and a gate contact is formed by filling the hole. The gate-top protection film has an opening exposing part of a portion of the area on the top surface of the gate electrode other than the region in contact with the gate contact. This facilitates external diffusion of hydrogen during annealing, or recovery from a fixed level and a damage layer during sintering.

Abstract: An inventive semiconductor device includes: a substrate; a plurality of first projections each including at least a gate electrode and formed on the substrate; and a plurality of second projections formed on the substrate. When a contour surface constituted by the uppermost face of the substrate and by side and upper faces of the first and second projections is measured for every partial area per unit area of the substrate, the maximum partial area of the contour surface is 1.6 or less times larger than the minimum partial area of the contour surface.

Abstract: An n-channel active region, a p-channel active region and an isolation insulating film are formed, and a silicon film is deposited via a gate insulating film. After introducing n-type impurities into the n-channel region and p-type impurities into the p-channel region, a silicon gate electrode is formed in such a manner that its width is enlarged only in the boundary portion between the n-channel region and the p-channel region. After forming a side wall insulating film, an n-channel diffusion layer and a p-channel diffusion layer, a metal silicide layer is formed in a self-aligned manner on the surfaces of the silicon gate electrode, the n-channel diffusion layer and the p-channel diffusion layer.

Abstract: After P+ ions are implanted into a polysilicon film in an nMOSFET region, a heat treatment is performed to diffuse phosphorus down to the lower part of the polysilicon film. The diffusion reduces the concentration of phosphorus in an upper end portion of the polysilicon film and inhibits the upper end edges of a gate electrode from being increased in size during patterning. Then, B+ ions are implanted into the polysilicon film in a pMOSFET region and the polysilicon film is etched into a gate configuration. Since a heat treatment for simultaneously diffusing phosphorus and boron in the polysilicon film is not performed, the entrance of boron from the gate electrode into a semiconductor substrate is inhibited, while the occurrence of side etching during the formation of an n-type polysilicon gate is suppressed.

Abstract: A conductive film for gate electrode including a polysilicon film is deposited on a semiconductor substrate, and patterned to form gate electrodes. An oxide film is formed on each side face of at least the polysilicon film, and by nitriding at least the surface portion of the oxide film, a nitride oxide film is formed on each side face of the gate electrodes. An interlayer insulating film is then deposited, and contact holes are formed through the interlayer insulating film. The existence of the nitride oxide film suppresses variation and reduction in size due to oxidation and etching of the gate side faces during resist removal and washing.

Abstract: A MOS transistor includes a gate oxide film, and a gate electrode which is formed by a lamination of first and second conductor films. A capacitive element includes a lower capacitive electrode formed of the first conductor film, a capacitive film made of an insulating film which is different from the gate oxide film, an upper capacitive electrode formed of the second conductor film on the capacitive film, and a leading electrode of the lower capacitive electrode formed of the second conductor film. At the same number of steps as in the case where the gate oxide film is used as the capacitive film, a semiconductor device can be manufactured with the capacitive film provided, the capacitive film being made of a nitride film or the like that is different from the gate oxide film. Consequently, a capacitive film having a great capacitance value per unit area is used so that the occupied area can be reduced and an increase in manufacturing cost can be controlled.

Abstract: A gate insulating film, a gate electrode, a gate-top protection film, LDD layers and nitride film sidewalls are formed on a semiconductor substrate. Source/drain regions are formed in the semiconductor substrate. After deposition of an interlayer insulating film on the resultant substrate, a hole is formed through the interlayer insulating film and the gate-top protection film to reach the gate electrode, and a gate contact is formed by filling the hole. The gate-top protection film has an opening exposing part of a portion of the area on the top surface of the gate electrode other than the region in contact with the gate contact. This facilitates external diffusion of hydrogen during annealing, or recovery from a fixed level and a damage layer during sintering.

Abstract: After phosphorus is ion implanted into a portion of a polysilicon film, first RTA is performed. After boron is ion implanted into another portion of the polysilicon film, the polysilicon film is patterned to form a gate electrode and a resistor film. A TEOS film is deposited and patterned to form a silicidation mask having an opening corresponding to a silicidation region. Thereafter, annealing for activating boron is performed in an atmosphere containing oxygen, thereby forming oxide films on a gate electrode and on heavily doped source/drain regions in the silicidation region. The oxide films suppress out-diffusion of the impurities and inhibit the impurity ions from penetrating the gate electrode 8 during ion implantation for promoting silicidation, which is performed subsequently.

Abstract: Gate insulating film, gate electrode made up of lower and upper gate electrodes, and on-gate passivation film are formed in this order on an Si substrate. Then, a sidewall is formed as a stack of an oxynitride sidewall having an L-shaped cross section and a nitride sidewall, so as to surround the gate electrode and on-gate passivation film. Alternatively, only the lower edge of an L-oxide sidewall may be changed into an oxynitride region. Or an oxide or stacked sidewall and a nitride sidewall, covering the oxide or stacked sidewall, may be formed instead of the oxynitride sidewall. In any of these embodiments, the lower edge of the sidewall is not removed during a wet etching process.

Abstract: An isolation which is higher in a stepwise manner than an active area of a silicon substrate is formed. On the active area, an FET including a gate oxide film, a gate electrode, a gate protection film, sidewalls and the like is formed. An insulating film is deposited on the entire top surface of the substrate, and a resist film for exposing an area stretching over the active area, a part of the isolation and the gate protection film is formed on the insulating film. There is no need to provide an alignment margin for avoiding interference with the isolation and the like to a region where a connection hole is formed. Since the isolation is higher in a stepwise manner than the active area, the isolation is prevented from being removed by over-etch in the formation of a connection hole to come in contact with a portion where an impurity concentration is low in the active area.

Abstract: A conductive film for gate electrode including a polysilicon film is deposited on a semiconductor substrate, and patterned to form gate electrodes. An oxide film is formed on each side face of at least the polysilicon film, and by nitriding at least the surface portion of the oxide film, a nitride oxide film is formed on each side face of the gate electrodes. An interlayer insulating film is then deposited, and contact holes are formed through the interlayer insulating film. The existence of the nitride oxide film suppresses variation and reduction in size due to oxidation and etching of the gate side faces during resist removal and washing.

Abstract: An isolation which is higher in a stepwise manner than an active area of a silicon substrate is formed. On the active area, an FET including a gate oxide film, a gate electrode, a gate protection film, sidewalls and the like is formed. An insulating film is deposited on the entire top surface of the substrate, and a resist film for exposing an area stretching over the active area, a part of the isolation and the gate protection film is formed on the insulating film. There is no need to provide an alignment margin for avoiding interference with the isolation and the like to a region where a connection hole is formed. Since the isolation is higher in a stepwise manner than the active area, the isolation is prevented from being removed by over-etch in the formation of a connection hole to come in contact with a portion where an impurity concentration is low in the active area.

Abstract: A plurality of metal wires are formed on an underlying interlayer insulating film. Areas among the metal wires are filled with a buried insulating film of a silicon oxide film with a small dielectric constant (i.e., a first dielectric film), and thus, a parasitic capacitance of the metal wires can be decreased. On the buried insulating film, a passivation film of a silicon nitride film with high moisture absorption resistance (i.e., a second dielectric film) is formed, and thus, a coverage defect can be avoided. A bonding pad is buried in an opening formed in a part of a surface protecting film including the buried insulating film and the passivation film, so as not to expose the buried insulating film within the opening. Thus, moisture absorption through the opening can be prevented.

Abstract: On a semiconductor substrate are successively deposited a silicon dioxide film and a silicon nitride film. The silicon nitride film, the silicon dioxide film, and the semiconductor substrate are sequentially etched using a photoresist film with an opening corresponding to an isolation region, thereby forming a trench. After depositing a diffusion preventing film, there is deposited an insulating film for isolation having reflowability. Although a void is formed in the insulating film for isolation in the isolation region, the insulating film for isolation is caused to reflow, thereby eliminating the void. After that, the whole substrate is planarized by CMP so as to remove the silicon nitride film and the silicon dioxide film, followed by the formation of gate insulating films, gate electrodes, sidewalls, and source/drain regions in respective element formation regions.

Abstract: A MOS transistor includes a gate oxide film, and a gate electrode which is formed by a lamination of first and second conductor films. A capacitive element includes a lower capacitive electrode formed of the first conductor film, a capacitive film made of an insulating film which is different from the gate oxide film, an upper capacitive electrode formed of the second conductor film on the capacitive film, and a leading electrode of the lower capacitive electrode formed of the second conductor film. At the same number of steps as in the case where the gate oxide film is used as the capacitive film, a semiconductor device can be manufactured with the capacitive film provided, the capacitive film being made of a nitride film or the like that is different from the gate oxide film. Consequently, a capacitive film having a great capacitance value per unit area is used so that the occupied area can be reduced and an increase in manufacturing cost can be controlled.

Abstract: An isolation is formed in a part of a P-well of a semiconductor substrate. A resistor film as a first conductor member is formed on the isolation. An insulating film covering the resistor film except for contact formation regions and an upper electrode film as a second conductor member are formed simultaneously with the formation of a gate electrode and a gate oxide film. Silicide films of a refractory metal are formed on the respective surfaces of the gate electrode, N-type high-concentration diffusion layers, the contact formation regions of the resistor film, and the upper electrode film. By utilizing a salicide process, a resistor and an inductor each occupying a small area can be formed without lowering the resistance of the resistor film. A capacitor, the resistor, and like component are selectively allowed to function.

Abstract: The fabricating method for semiconductor devices in which the trench technique is employed to perform isolation between devices, and which comprises the steps of sequentially depositing a first film 2, 3 and a second film 4 on top of a silicon substrate 1, forming an element isolation trench 5 in the silicon substrate 1 with masking of the first film 2, 3 and second film 4 which have undergone patterning, and growing a silicon oxide film 6 that is generated by reaction of ozone and tetra-ethyl-ortho-silicate inside the element isolation trench where silicon is exposed.

Abstract: The top surface of a substrate in a peripheral circuit region is at a level that is higher than the top surface of the substrate in a memory cell region and that is substantially equal to the top surface of a floating gate electrode. A control gate electrode is formed on the floating gate electrode via a gate insulator film, and a gate electrode is formed on the substrate in the peripheral circuit region via a gate insulator film. The top surface of a buried insulator film for trench isolation may be at a level equal to the top surface of the floating gate electrode or to the top surface of an underlying film if the control gate electrode is formed of a multi-layer film. A level difference between the control gate electrode in the memory cell region and the gate electrode in the peripheral circuit region can be reduced, and thus fine patterns can be formed in these regions.

Abstract: A plurality of metal wires are formed on an underlying interlayer insulating film. Areas among the metal wires are filled with a buried insulating film of a silicon oxide film with a small dielectric constant (i.e., a first dielectric film), and thus, a parasitic capacitance of the metal wires can be decreased. On the buried insulating film, a passivation film of a silicon nitride film with high moisture absorption resistance (i.e., a second dielectric film) is formed, and thus, a coverage defect can be avoided. A bonding pad is buried in an opening formed in a part of a surface protecting film including the buried insulating film and the passivation film, so as not to expose the buried insulating film within the opening. Thus, moisture absorption through the opening can be prevented.