Patents by Inventor Mladenko Vukic

Mladenko Vukic has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9891269
    Abstract: An integrated circuit die has one or more through-body-vias and a testing circuit on board the die which tests for defects in a through-body-via by driving of pulses of current into a node. Pulses are counted until the voltage of the node reaches a threshold voltage to provide a pulse count which is a function of the capacitance of the node. A determination is made as to whether the through-body-via of the node has a defect as a function of the pulse count.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: February 13, 2018
    Assignee: INTEL CORPORATION
    Inventors: Kalyan C. Kolluru, Mladenko Vukic
  • Patent number: 9551741
    Abstract: Current tests for I/O interface connectors are described. In one example a test may include applying a forced energy to a first pin of an interface of a data communications bus of an integrated circuit on a die, sensing the energy caused by the forced energy at a second pin of the interface, and comparing the forced energy and the sensed energy to determine an amount of current leaked by at least a portion of the interface.
    Type: Grant
    Filed: November 23, 2011
    Date of Patent: January 24, 2017
    Assignee: Intel Corporation
    Inventors: Bharani Thiruvengadam, Mladenko Vukic, Tak M. Mak
  • Patent number: 9513330
    Abstract: In accordance with one aspect of the present description, an integrated circuit die has a plurality of through-body-vias and a testing circuit on board the die which allows charges on a first and second through-body-via to redistribute between them to provide an indication whether one or both of the first and second through-body-vias has a defect. Other aspects are described.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: December 6, 2016
    Assignee: INTEL CORPORATION
    Inventors: Mladenko Vukic, Kalyan C. Kolluru
  • Publication number: 20150160289
    Abstract: In accordance with one aspect of the present description, an integrated circuit die has a one or more through-body-vias and a testing circuit on board the die which tests for defects in a through-body-via by driving of pulses of current into a node. Pulses are counted until the voltage of the node reaches a threshold voltage to provide a pulse count which is a function of the capacitance of the node. A determination is made as to whether the through-body-via of the node has a defect as a function of the pulse count. Other aspects are described.
    Type: Application
    Filed: June 29, 2012
    Publication date: June 11, 2015
    Inventors: Kalyan C. Kolluru, Mladenko Vukic
  • Publication number: 20140070838
    Abstract: In accordance with one aspect of the present description, an integrated circuit die has a plurality of through-body-vias and a testing circuit on board the die which allows charges on a first and second through-body-via to redistribute between them to provide an indication whether one or both of the first and second through-body-vias has a defect. Other aspects are described.
    Type: Application
    Filed: June 29, 2012
    Publication date: March 13, 2014
    Inventors: Mladenko Vukic, Kalyan C. Kolluru
  • Publication number: 20130271167
    Abstract: Current tests for I/O interface connectors are described. In one example a test may include applying a forced energy to a first pin of an interface of a data communications bus of an integrated circuit on a die, sensing the energy caused by the forced energy at a second pin of the interface, and comparing the forced energy and the sensed energy to determine an amount of current leaked by at least a portion of the interface.
    Type: Application
    Filed: November 23, 2011
    Publication date: October 17, 2013
    Inventors: Bharani Thiruvengadam, Mladenko Vukic, Tak M. Mak
  • Publication number: 20050172091
    Abstract: A method and an apparatus to process read data return has been disclosed. In one embodiment, the method includes packing a cache line of each of a number of read data returns into one or more packets, splitting each of the one or more packets into a plurality of flits, and interleaving the plurality of flits of each of the plurality of read data returns. Other embodiments are described and claimed.
    Type: Application
    Filed: January 29, 2004
    Publication date: August 4, 2005
    Inventors: Hemant Rotithor, An-Chow Lai, Randy Osborne, Olivier Maquelin, Mladenko Vukic