Patents by Inventor Mo Liu
Mo Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20260151756Abstract: Provided herein is a method for preparing a catalyst form recycled waste batteries, which includes the preparation of a NiCoMnOx composite oxide, and further extends to the preparation of a perovskite catalyst and a core-shell loaded noble catalyst.Type: ApplicationFiled: December 3, 2024Publication date: June 4, 2026Inventors: Wei Gong, Mo Liu, Yang Dai, Zhen Yao
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Patent number: 12563686Abstract: An apparatus and method for reducing differential cross-talk in a pin arrangement of a socket are described. Socket pins within a differential pair use a modified shape to tighten the intra-pair pin coupling to reduce the crosstalk without changing the pin map. The middle vertical segment of one pin of a diagonally adjacent differential pin pair is modified to be closer to the other pin than other corresponding locations of the pins. The spring beam that extends from the middle vertical segment of the one pin is modified to accommodate the package landing pad that the spring beam contacts to maintain a uniform pitch.Type: GrantFiled: April 25, 2022Date of Patent: February 24, 2026Assignee: Intel CorporationInventors: Xiang Li, Shaohua Li, Landon Hanks, Kai Xiao, Mo Liu, Jingbo Li
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Patent number: 12469993Abstract: In one embodiment, a card edge connector includes a housing including a slot to receive a first circuit board. A first plurality of pins extend from within the slot through a bottom of the housing. Each of the first plurality of pins includes a first end to mate with a corresponding contact of the first circuit board and a second end to mate with a corresponding one of a first plurality of contacts of a second circuit board, the second end including a heel portion and a toe portion extending from the heel portion in a direction away from a centerline of the slot. A second plurality of pins extend from within the slot through the bottom of the housing.Type: GrantFiled: September 24, 2021Date of Patent: November 11, 2025Assignee: Intel CorporationInventors: Xiang Li, Shaohua Li, Kai Xiao, Mo Liu, Jingbo Li
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Publication number: 20250311090Abstract: Methods, systems, apparatus, and articles of manufacture to reduce crosstalk in integrated circuit packages are disclosed. An example apparatus includes a package substrate, a conductive via extending between first and second surfaces of the package substrate, a metal casing extending between the first and second surfaces, the metal casing surrounding the conductive via, and a dielectric material positioned between the conductive via and the metal casing.Type: ApplicationFiled: March 26, 2024Publication date: October 2, 2025Inventors: Shaohua Li, Carlos Alberto Lizalde Moreno, Kai Xiao, Raul Enriquez Shibayama, Vijaya Kumar Boddu, Sri Chaitra Jyotsna Chavali, Mo Liu
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Patent number: 12341279Abstract: In one embodiment, a card edge connector includes: a housing having an opening into which a first circuit board is to be inserted; a plurality of pins each having a first end and a second end, the plurality of pins extending from within the opening through a bottom surface of the housing, the first end of the first plurality of pins to mate with a corresponding contact of the first circuit board; and a plurality of ball grid array (BGA) solder balls each adapted at the second end of a corresponding one of the plurality of pins, the plurality of pins to mate with a corresponding conductive area of a second circuit board to which the card edge connector mates via the plurality of BGA solder balls. Other embodiments are described and claimed.Type: GrantFiled: March 16, 2021Date of Patent: June 24, 2025Inventors: Xiang Li, Mo Liu, Shaohua Li, Jingbo Li, Kai Xiao
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Publication number: 20250086202Abstract: Systems, methods and computer-readable memory devices are provided for greater efficiency in the configuration of a database cluster for performing a query workload. A database cluster configuration system is provided that includes a database cluster comprising one or more compute resources configured to perform database queries. A query workload comprising a plurality of queries is received. An initial workload-level configuration is applied. For each query of the query workload, a query-level configuration is generated using a query configuration model corresponding to each query in a contextual Bayesian optimization with centroid learning while also leveraging the query plan for each executing query for query characterization and including application of virtual operators. Query events are collected and used to update the corresponding query configuration model. The workload-level configuration is updated based on the query events and cached for use during a subsequent execution of the workload.Type: ApplicationFiled: September 13, 2023Publication date: March 13, 2025Inventors: Yiwen ZHU, Subramaniam Venkatraman KRISHNAN, Weihan TANG, Tengfei HUANG, Rui FANG, Rahul Kumar CHALLAPALLI, Mo LIU, Long TIAN, Karuna Sagar KRISHNA, Estera Zaneta KOT, Xin HE, Ashit R. GOSALIA, Dario Kikuchi BERNAL, Aditya LAKRA, Arshdeep SEKHON, Sule KAHRAMAN, Carlo Aldo CURINO, Brian Paul KROTH, Rathijit SEN, Andreas Christian MUELLER, Shaily Jignesh FOZDAR, Dhruv Harendra RELWANI, Xiang LI, Sergiy MATUSEVYCH
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Publication number: 20240220855Abstract: A total demand model can be trained, by machine learning and using historical data. The total demand model can be configured to process current data and output first data indicating a predicted future total demand for a product. A target demand model can be trained. The target demand model can be configured to process the current data and, based on processing the current data, output a plurality of class demand models. Each class demand model can be configured to predict demand, for each of a plurality of future time periods, for a plurality of classes of the product. The class demand models configured to optimize, for each of the plurality of future time periods, a respective set of optimal prices for the respective classes of the product that maximizes total expected revenue for the product over the plurality of classes of the product.Type: ApplicationFiled: December 30, 2022Publication date: July 4, 2024Inventors: Zhengliang Xue, Mo Liu, Shivaram Subramanian, Markus Ettl
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Publication number: 20230318211Abstract: Methods and apparatus relating to liquid-proof edge connector solutions for immersion cooling are described. In one embodiment, a seal prevents a cooling liquid to cause electrical contact with a pin of an edge card to be inserted in a connector. And, an adhesive prevents the cooling liquid to cause electrical contact with a terminal of the connector. Other embodiments are also claimed and disclosed.Type: ApplicationFiled: April 3, 2023Publication date: October 5, 2023Applicant: Intel CorporationInventors: Xiang Li, Shaohua Li, Jingbo Li, Mo Liu, Kai Xiao, Kai Wang
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Publication number: 20230046581Abstract: An apparatus and method for reducing differential cross-talk in a pin arrangement of a socket are described. Socket pins within a differential pair use a modified shape to tighten the intra-pair pin coupling to reduce the crosstalk without changing the pin map. The middle vertical segment of one pin of a diagonally adjacent differential pin pair is modified to be closer to the other pin than other corresponding locations of the pins. The spring beam that extends from the middle vertical segment of the one pin is modified to accommodate the package landing pad that the spring beam contacts to maintain a uniform pitch.Type: ApplicationFiled: April 25, 2022Publication date: February 16, 2023Inventors: Xiang Li, Shaohua Li, Landon Hanks, Kai Xiao, Mo Liu, Jingbo Li
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Publication number: 20220021139Abstract: In one embodiment, a card edge connector includes a housing including a slot to receive a first circuit board. A first plurality of pins extend from within the slot through a bottom of the housing. Each of the first plurality of pins includes a first end to mate with a corresponding contact of the first circuit board and a second end to mate with a corresponding one of a first plurality of contacts of a second circuit board, the second end including a heel portion and a toe portion extending from the heel portion in a direction away from a centerline of the slot. A second plurality of pins extend from within the slot through the bottom of the housing.Type: ApplicationFiled: September 24, 2021Publication date: January 20, 2022Inventors: Xiang Li, Shaohua Li, Kai Xiao, Mo Liu, Jingbo Li
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Publication number: 20210203094Abstract: In one embodiment, a card edge connector includes: a housing having an opening into which a first circuit board is to be inserted; a plurality of pins each having a first end and a second end, the plurality of pins extending from within the opening through a bottom surface of the housing, the first end of the first plurality of pins to mate with a corresponding contact of the first circuit board; and a plurality of ball grid array (BGA) solder balls each adapted at the second end of a corresponding one of the plurality of pins, the plurality of pins to mate with a corresponding conductive area of a second circuit board to which the card edge connector mates via the plurality of BGA solder balls. Other embodiments are described and claimed.Type: ApplicationFiled: March 16, 2021Publication date: July 1, 2021Inventors: Xiang Li, Mo Liu, Shaohua Li, Jingbo Li, Kai Xiao
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Patent number: 10965047Abstract: Embodiments may relate to a connector. The connector may include a plurality of connector pins that are to communicatively couple an element of a printed circuit board (PCB) with an element of an electronic device when the element of the PCB and the element of the electronic device are coupled with the connector. The connector may also include an active circuit that is communicatively coupled with a pin of the plurality of pins. The active circuit may be configured to match an impedance of the element of the PCB with an impedance of the element of the electronic device. Other embodiments may be described or claimed.Type: GrantFiled: June 4, 2019Date of Patent: March 30, 2021Assignee: Intel CorporationInventors: Jong-Ru Guo, Yunhui Chu, Jun Liao, Kai Xiao, Jingbo Li, Yuanhong Zhao, Mo Liu, Beomtaek Lee, James A. McCall, Jaejin Lee, Xiaoning Ye, Zuoguo Wu, Xiang Li
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Publication number: 20200083155Abstract: Apparatuses, systems and methods associated with electrical routing layout of printed circuit boards and integrated circuit substrates are disclosed herein. In embodiments, an apparatus includes a first electrically conductive path that extends through a region, wherein the first electrically conductive path includes a first pad located at a surface of the region, a first via that extends through the region, and a first trace that extends in a first direction. The apparatus further includes a second electrically conductive path that extends through the region, wherein the second electrically conductive path includes a second pad located at the surface and adjacent to the first pad, a second via that extends through the region, and a second trace that extends in a second direction. Other embodiments may be described and/or claimed.Type: ApplicationFiled: September 11, 2018Publication date: March 12, 2020Inventors: Raul ENRIQUEZ SHIBAYAMA, Vijaya BODDU, Luis Nathan PEREZ ACOSTA, Francisco Javier GALARZA MEDINA, Kai XIAO, Luis ROSALES-GALVAN, Beom-Taek LEE, Carlos Alberto LIZALDE MORENO, Gaudencio HERNANDEZ SOSA, Mo LIU
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Publication number: 20190288421Abstract: Embodiments may relate to a connector. The connector may include a plurality of connector pins that are to communicatively couple an element of a printed circuit board (PCB) with an element of an electronic device when the element of the PCB and the element of the electronic device are coupled with the connector. The connector may also include an active circuit that is communicatively coupled with a pin of the plurality of pins. The active circuit may be configured to match an impedance of the element of the PCB with an impedance of the element of the electronic device. Other embodiments may be described or claimed.Type: ApplicationFiled: June 4, 2019Publication date: September 19, 2019Applicant: Intel CorporationInventors: Jong-Ru Guo, Yunhui Chu, Jun Liao, Kai Xiao, Jingbo Li, Yuanhong Zhao, Mo Liu, Beomtaek Lee, James A. McCall, Jaejin Lee, Xiaoning Ye, Zuoguo Wu, Xiang Li
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Patent number: 10076024Abstract: This disclosure relates generally to an electronic assembly and method having a first electrical connection point and a second electrical connection point and a differential interconnect coupling the first electrical connection point to the second electrical connection point, the differential interconnect including first and second transmission traces including a interior edges and a exterior edges opposite the interior edges, the second interior edge facing the first interior edge, and stub traces, each stub trace coupled to one of the first and second transmission traces and projecting from one of the first interior edge, the first exterior edge, the second interior edge, and the second exterior edge. A substantially equal number of stub traces project from the first exterior edge and the second exterior edge. At least twice as many stub traces project from the first and second exterior edges as project from the first and second interior edges.Type: GrantFiled: June 28, 2016Date of Patent: September 11, 2018Assignee: Intel CorporationInventors: Ruihua Ding, Min Wang, Mo Liu
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Patent number: 9767427Abstract: One embodiment is a method that builds a model of multi-dimensional sequence data in real-time with cuboids that aggregate the multi-dimensional sequence data over both patterns and dimensions. The model provides search results for a query.Type: GrantFiled: April 30, 2009Date of Patent: September 19, 2017Assignee: Hewlett Packard Enterprise Development LPInventors: Mo Liu, Song Wang, Chetan Kumar Gupta, Ismail Ari, Abhay Mehta
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Publication number: 20170033425Abstract: This disclosure relates generally to an electronic assembly and method having a first electrical connection point and a second electrical connection point and a differential interconnect coupling the first electrical connection point to the second electrical connection point, the differential interconnect including first and second transmission traces including a interior edges and a exterior edges opposite the interior edges, the second interior edge facing the first interior edge, and stub traces, each stub trace coupled to one of the first and second transmission traces and projecting from one of the first interior edge, the first exterior edge, the second interior edge, and the second exterior edge. A substantially equal number of stub traces project from the first exterior edge and the second exterior edge. At least twice as many stub traces project from the first and second exterior edges as project from the first and second interior edges.Type: ApplicationFiled: June 28, 2016Publication date: February 2, 2017Inventors: Ruihua Ding, Min Wang, Mo Liu
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Publication number: 20160203185Abstract: There is provided a computer-implemented method of determining an execution ordering. An exemplary method comprises generating a directed graph based on a hierarchy. The hierarchy includes a plurality of pattern queries. The method also includes determining a minimum spanning tree of the directed graph. The method further includes determining an execution order of the pattern queries based on the minimum spanning tree.Type: ApplicationFiled: March 18, 2016Publication date: July 14, 2016Inventors: Chetan Kumar Gupta, Song Wang, Abhay Mehta, Mo Liu, Elke A. Rundensteiner
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Patent number: 9386690Abstract: This disclosure relates generally to an electronic assembly and method having a first electrical connection point and a second electrical connection point and a differential interconnect coupling the first electrical connection point to the second electrical connection point, the differential interconnect including first and second transmission traces including a interior edges and a exterior edges opposite the interior edges, the second interior edge facing the first interior edge, and stub traces, each stub trace coupled to one of the first and second transmission traces and projecting from one of the first interior edge, the first exterior edge, the second interior edge, and the second exterior edge. A substantially equal number of stub traces project from the first exterior edge and the second exterior edge. At least twice as many stub traces project from the first and second exterior edges as project from the first and second interior edges.Type: GrantFiled: March 27, 2014Date of Patent: July 5, 2016Assignee: Intel CorporationInventors: Ruihua Ding, Min Wang, Mo Liu
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Patent number: 9305058Abstract: There is provided a computer-implemented method of determining an execution ordering. An exemplary method comprises generating a directed graph based on a hierarchy. The hierarchy includes a plurality of pattern queries. The method also includes determining a minimum spanning tree of the directed graph. The method further includes determining an execution order of the pattern queries based on the minimum spanning tree.Type: GrantFiled: October 31, 2011Date of Patent: April 5, 2016Assignee: Hewlett Packard Enterprise Development LPInventors: Chetan Kumar Gupta, Song Wang, Abhay Mehta, Mo Liu, Elke A. Rundensteiner