Abstract: An apparatus and method for issue grouping of instructions in a VLIW processor is disclosed. There can be one, two, or three issue groups (but no greater than three issue groups) in each VLIW packet. In one embodiment, a template in the VLIW packet comprises two issue group end markers where each issue group end marker comprises three bits. The three bits in the first issue group end marker identifies the instruction which is the last instruction in the first issue group. Likewise, the three bits in the second issue group end marker identifies the instruction which is the last instruction in the second issue group. Any instructions in the VLIW packet falling outside the two expressly defined first and second issue groups are placed in a third issue group. As such, three issue groups can be identified by use of the two issue group end markers. In one embodiment, the template of the VLIW packet includes a chaining bit.

Abstract: The present invention provides a new programming language which. is a superset of C++ optimized for writing vectorized dual-threaded programs on the MSP media processor. This invention discloses novel language constructs in the syntax and semantics to facilitate efficient programming and the generation of optimized efficient MSP object code. We have invented in VIVID new data types such as VECTOR and GMASK as well as new operators that map directly into the MSP instruction set such as @shfl, @avg, etc. We have also extended C++ to facilitate dual-threaded execution by exposing the MSP's fork-join model to the VIVID programmer via. adding fork-join constructs to VIVID. We have also invented a syntax and semantics to facilitate having multiple returned results from a vector operation such as VD @@ VC=VA @shfl VB.

Abstract: Multiple processor circuit simulator comprising a debugger interface, a synchronizer, a RISC processor simulator, a vector processor simulator, a shared memory, a co-processor interface module and an events module. The multiple processor simulator tightly couples the RISC processor simulator and vector processor simulator into a single executable process and a single address space. The synchronizer interleaves simulation of instruction execution between multiple processor simulators. The synchronizer determines which processor simulator to execute based on a furthest-behind clocking scheme. The clocking scheme is implemented by comparing the values held in clock simulators corresponding to the processor simulators.