Patents by Inventor Moazzem Hossain
Moazzem Hossain has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11778515Abstract: A wireless communication network serves user communication devices using Internet Protocol (IP) and Integrated Access and Backhaul (IAB). An IAB Mobile Termination (MT) and an IAB donor establish a wireless IAB link. The IAB MT and a Centralized Unit (CU) establish IP links over the wireless IAB link. The IP links have different QoS levels. The IAB MT exchanges data streams with the user communication devices. The data streams have different QoS requirements. The IAB MT and the CU correlate the QoS requirements of the data streams with the QoS levels of the IP links. The IAB MT and the CU exchange individual ones of the data streams over individual ones of the IP links based on the QoS correlations. The CU exchanges the data streams with a data communication network based on the QoS requirements.Type: GrantFiled: April 26, 2021Date of Patent: October 3, 2023Assignee: T-MOBILE INNOVATIONS LLCInventors: David Z. Sun, Kristian Kai Johns, Jay Ronald Chernoff, Charles Anthony Manganiello, Akm Moazzem Hossain, Charles D. Todd, Gopal K. Sood
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Publication number: 20230225217Abstract: A method of manufacturing one or more interconnects to magnetoresistive structure comprising (i) depositing a first conductive material in a via; (2) etching the first conductive material wherein, after etching the first conductive material a portion of the first conductive material remains in the via, (3) partially filling the via by depositing a second conductive material in the via and directly on the first conductive material in the via; (4) depositing a first electrode material in the via and directly on the second conductive material in the via; (5) polishing a first surface of the first electrode material wherein, after polishing, the first electrode material is (i) on the second conductive material in the via and (ii) over the portion of the first conductive material remaining in the via; and (6) forming a magnetoresistive structure over the first electrode material.Type: ApplicationFiled: March 16, 2023Publication date: July 13, 2023Applicant: Everspin Technologies, Inc.Inventors: Kerry Joseph NAGEL, Kenneth SMITH, Moazzem HOSSAIN, Sanjeev AGGARWAL
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Patent number: 11631806Abstract: A method of manufacturing one or more interconnects to magnetoresistive structure comprising (i) depositing a first conductive material in a via; (2) etching the first conductive material wherein, after etching the first conductive material a portion of the first conductive material remains in the via, (3) partially filling the via by depositing a second conductive material in the via and directly on the first conductive material in the via; (4) depositing a first electrode material in the via and directly on the second conductive material in the via; (5) polishing a first surface of the first electrode material wherein, after polishing, the first electrode material is (i) on the second conductive material in the via and (ii) over the portion of the first conductive material remaining in the via; and (6) forming a magnetoresistive structure over the first electrode material.Type: GrantFiled: May 11, 2021Date of Patent: April 18, 2023Assignee: EVERSPIN TECHNOLOGIES, INC.Inventors: Kerry Joseph Nagel, Kenneth Smith, Moazzem Hossain, Sanjeev Aggarwal
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Publication number: 20220345944Abstract: A wireless communication network serves user communication devices using Internet Protocol (IP) and Integrated Access and Backhaul (IAB). An IAB Mobile Termination (MT) and an IAB donor establish a wireless IAB link. The IAB MT and a Centralized Unit (CU) establish IP links over the wireless IAB link. The IP links have different QoS levels. The IAB MT exchanges data streams with the user communication devices. The data streams have different QoS requirements. The IAB MT and the CU correlate the QoS requirements of the data streams with the QoS levels of the IP links. The IAB MT and the CU exchange individual ones of the data streams over individual ones of the IP links based on the QoS correlations. The CU exchanges the data streams with a data communication network based on the QoS requirements.Type: ApplicationFiled: April 26, 2021Publication date: October 27, 2022Inventors: David Z. Sun, Kristian Kai Johns, Jay Ronald Chernoff, Charles Anthony Manganiello, Akm Moazzem Hossain, Charles D. Todd, Gopal K. Sood
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Patent number: 11371976Abstract: A sensor system in a package, comprising: a package, the package including: a sensor chip comprising sensor array comprising a plurality of sensing elements, wherein each of the plurality of sensing elements are functionalized with a deposited mixture consisting of hybrid nanostructures and a molecular formulation specifically targeting at least one of a plurality of gases, and wherein each of the plurality of sensing elements comprises a resistance and a capacitance, and wherein at least one resistance and capacitance are altered when the interacting with gaseous chemical compounds; and a mixed signal System on a Chip (SoC), comprising an analog signal conditioning and Analog-to-Digital conversion circuit configured to convert the analog signal into a digital signal, and a low-power processor circuit configured to processes the digital signal using a pattern recognition system implementing gas detection and measurement algorithms.Type: GrantFiled: April 24, 2020Date of Patent: June 28, 2022Assignee: AERNOS, INC.Inventors: Sundip R. Doshi, Moazzem Hossain, Herve Lambert, Albert Chen
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Publication number: 20210357227Abstract: A micro-controller unit (MCU) for low power IoT and edge computing applications is disclosed. MCU includes instruction fetching module configured to fetch instruction from instruction memory, instruction decoding module configured to decode instruction to obtain decoded instruction, and execution module including first and second execution units and clock gating circuit. Second execution unit is configured to execute instruction types. Execution module is configured to receive instruction from instruction decoding module and execute decoded instruction via particular logic circuit from first logic circuits associated with first execution unit. First logic circuits except the particular logic circuit are turned-off during execution via clock gating circuit.Type: ApplicationFiled: May 11, 2021Publication date: November 18, 2021Inventors: Md. Ashraful ISLAM, Seiji MIWA, Moazzem HOSSAIN
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Publication number: 20210280778Abstract: A method of manufacturing one or more interconnects to magnetoresistive structure comprising (i) depositing a first conductive material in a via; (2) etching the first conductive material wherein, after etching the first conductive material a portion of the first conductive material remains in the via, (3) partially filling the via by depositing a second conductive material in the via and directly on the first conductive material in the via; (4) depositing a first electrode material in the via and directly on the second conductive material in the via; (5) polishing a first surface of the first electrode material wherein, after polishing, the first electrode material is (i) on the second conductive material in the via and (ii) over the portion of the first conductive material remaining in the via; and (6) forming a magnetoresistive structure over the first electrode material.Type: ApplicationFiled: May 11, 2021Publication date: September 9, 2021Applicant: Everspin Technologies, Inc.Inventors: Kerry Joseph NAGEL, Kenneth SMITH, Moazzem HOSSAIN, Sanjeev AGGARWAL
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Publication number: 20210247368Abstract: A novel approach, based on hybrid nanostructure gas sensors, to correlate metrics related to specific medical conditions to a signature created by the sensor's response to the Volatile Organic Compounds (VOCs) contained in human breath.Type: ApplicationFiled: April 15, 2021Publication date: August 12, 2021Inventors: Sundip R. DOSHI, Heng Chia SU, Albert CHEN, Alexey VARGANOV, Moazzem HOSSAIN, Herve LAMBERT
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Publication number: 20210247342Abstract: A device, comprising: an enclosure; a module within the disclosure, the module comprising: a package, the package including: a sensor chip comprising sensor array comprising a plurality of sensing elements, wherein each of the plurality of sensing elements are functionalized with a deposited mixture consisting of hybrid nanostructures and a molecular formulation specifically targeting at least one of a plurality of gases, and wherein each of the plurality of sensing elements comprises a resistance and a capacitance, and wherein at least one resistance and capacitance are altered when the interacting with gaseous chemical compounds, and a mixed signal System on a Chip (SoC), comprising an analog signal conditioning and Analog-to-Digital conversion circuit configured to convert the analog signal into a digital signal, and a low-power processor circuit configured to processes the digital signal using a pattern recognition system implementing gas detection and measurement algorithms; and a particulate matter sensType: ApplicationFiled: April 27, 2021Publication date: August 12, 2021Inventors: Sundip R. DOSHI, Moazzem HOSSAIN, Herve LAMBERT, Albert CHEN
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Patent number: 11031546Abstract: A method of manufacturing one or more interconnects to magnetoresistive structure comprising (i) depositing a first conductive material in a via; (2) etching the first conductive material wherein, after etching the first conductive material a portion of the first conductive material remains in the via, (3) partially filling the via by depositing a second conductive material in the via and directly on the first conductive material in the via; (4) depositing a first electrode material in the via and directly on the second conductive material in the via; (5) polishing a first surface of the first electrode material wherein, after polishing, the first electrode material is (i) on the second conductive material in the via and (ii) over the portion of the first conductive material remaining in the via; and (6) forming a magnetoresistive structure over the first electrode material.Type: GrantFiled: November 19, 2018Date of Patent: June 8, 2021Assignee: Everspin Technologies, Inc.Inventors: Kerry Joseph Nagel, Kenneth H. Smith, Moazzem Hossain, Sanjeev Aggarwal
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Publication number: 20200256840Abstract: A sensor system in a package, comprising: a package, the package including: a sensor chip comprising sensor array comprising a plurality of sensing elements, wherein each of the plurality of sensing elements are functionalized with a deposited mixture consisting of hybrid nanostructures and a molecular formulation specifically targeting at least one of a plurality of gases, and wherein each of the plurality of sensing elements comprises a resistance and a capacitance, and wherein at least one resistance and capacitance are altered when the interacting with gaseous chemical compounds; and a mixed signal System on a Chip (SoC), comprising an analog signal conditioning and Analog-to-Digital conversion circuit configured to convert the analog signal into a digital signal, and a low-power processor circuit configured to processes the digital signal using a pattern recognition system implementing gas detection and measurement algorithms.Type: ApplicationFiled: April 24, 2020Publication date: August 13, 2020Inventors: Sundip R. DOSHI, Moazzem HOSSAIN, Herve LAMBERT, Albert CHEN
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Publication number: 20200064294Abstract: A gas sensor architecture and implementation, based on hybrid nanostructures, combining a plurality of inter-dependent technologies, including chemical engineering and material science, embedded electronics at board and IC level, MEMS, data science, mobile and Cloud-based applications, to deliver a combination of performance and functional attributes in a solution that is manufacturable in very high volume and will enable the collection of highly granular information related to the presence and concentration of target gases in ambient air.Type: ApplicationFiled: August 21, 2019Publication date: February 27, 2020Inventors: Sundip R. DOSHI, Heng Chia SU, Albert CHEN, Alexey VARGANOV, Moazzem HOSSAIN, Herve LAMBERT
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Patent number: 10541362Abstract: The present disclosure is drawn to, among other things, a method of fabricating an integrated circuit device having a magnetoresistive device. In some aspects, the method includes forming the magnetoresistive device on a first contact of a substrate, wherein the magnetoresistive device includes a fixed magnetic region and a free magnetic region separated by an intermediate region; depositing a first dielectric material over the magnetoresistive device; depositing a second dielectric material over the first dielectric material; polishing a surface of the second dielectric material; forming a first cavity through the polished surface of the second dielectric material to expose a surface of the magnetoresistive device; and depositing an electrically conductive material in the first cavity to form a via.Type: GrantFiled: April 10, 2019Date of Patent: January 21, 2020Assignee: Everspin Technologies, Inc.Inventors: Sarin A. Deshpande, Sanjeev Aggarwal, Moazzem Hossain
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Publication number: 20190237665Abstract: The present disclosure is drawn to, among other things, a method of fabricating an integrated circuit device having a magnetoresistive device. In some aspects, the method includes forming the magnetoresistive device on a first contact of a substrate, wherein the magnetoresistive device includes a fixed magnetic region and a free magnetic region separated by an intermediate region; depositing a first dielectric material over the magnetoresistive device; depositing a second dielectric material over the first dielectric material; polishing a surface of the second dielectric material; forming a first cavity through the polished surface of the second dielectric material to expose a surface of the magnetoresistive device; and depositing an electrically conductive material in the first cavity to form a via.Type: ApplicationFiled: April 10, 2019Publication date: August 1, 2019Applicant: Everspin Technologies, Inc.Inventors: Sarin A. DESHPANDE, Sanjeev AGGARWAL, Moazzem HOSSAIN
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Patent number: 10297747Abstract: The present disclosure is drawn to, among other things, a method of fabricating an integrated circuit device having a magnetoresistive device. In some aspects, the method includes forming the magnetoresistive device on a first contact of a substrate, wherein the magnetoresistive device includes a fixed magnetic region and a free magnetic region separated by an intermediate region; depositing a first dielectric material over the magnetoresistive device; depositing a second dielectric material over the first dielectric material; polishing a surface of the second dielectric material; forming a first cavity through the polished surface of the second dielectric material to expose a surface of the magnetoresistive device; and depositing an electrically conductive material in the first cavity to form a via.Type: GrantFiled: April 20, 2018Date of Patent: May 21, 2019Assignee: Everpsin Technologies, Inc.Inventors: Sarin A. Deshpande, Sanjeev Aggarwal, Moazzem Hossain
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Publication number: 20190103555Abstract: A method of manufacturing one or more interconnects to magnetoresistive structure comprising (i) depositing a first conductive material in a via; (2) etching the first conductive material wherein, after etching the first conductive material a portion of the first conductive material remains in the via, (3) partially filling the via by depositing a second conductive material in the via and directly on the first conductive material in the via; (4) depositing a first electrode material in the via and directly on the second conductive material in the via; (5) polishing a first surface of the first electrode material wherein, after polishing, the first electrode material is (i) on the second conductive material in the via and (ii) over the portion of the first conductive material remaining in the via; and (6) forming a magnetoresistive structure over the first electrode material.Type: ApplicationFiled: November 19, 2018Publication date: April 4, 2019Applicant: Everspin Technologies, Inc.Inventors: Kerry Joseph NAGEL, Kenneth H. SMITH, Moazzem HOSSAIN, Sanjeev AGGARWAL
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Patent number: 10164176Abstract: A method of manufacturing one or more interconnects to a magnetoresistive structure, the method comprising depositing a first conductive material (i) in a via which is formed through a first surface of a first dielectric layer and (ii) directly on the first surface of the first dielectric layer. The method further includes etching the first conductive material wherein, after etching the first conductive material, a portion of the first conductive material remains (i) in the via and (ii) directly on the first surface of the first dielectric layer. The method also includes partially filling the via by depositing a second conductive material (i) in the via and (ii) directly on the first conductive material remaining in the via, depositing a first electrode material (i) in the via and (ii) directly on the second conductive material which is in the via, and forming a magnetoresistive structure over the first electrode material.Type: GrantFiled: January 6, 2017Date of Patent: December 25, 2018Assignee: Everspin Technologies, Inc.Inventors: Kerry Joseph Nagel, Kenneth Smith, Moazzem Hossain, Sanjeev Aggarwal
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Publication number: 20180309051Abstract: The present disclosure is drawn to, among other things, a method of fabricating an integrated circuit device having a magnetoresistive device. In some aspects, the method includes forming the magnetoresistive device on a first contact of a substrate, wherein the magnetoresistive device includes a fixed magnetic region and a free magnetic region separated by an intermediate region; depositing a first dielectric material over the magnetoresistive device; depositing a second dielectric material over the first dielectric material; polishing a surface of the second dielectric material; forming a first cavity through the polished surface of the second dielectric material to expose a surface of the magnetoresistive device; and depositing an electrically conductive material in the first cavity to form a via.Type: ApplicationFiled: April 20, 2018Publication date: October 25, 2018Applicant: Everspin Technologies, Inc.Inventors: Sarin A. DESHPANDE, Sanjeev AGGARWAL, Moazzem HOSSAIN
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Patent number: 9728583Abstract: A layer of silicon nitride above the bottom electrode and on the sidewalls of the magnetoresistive stack serves as an insulator and an etch stop during manufacturing of a magnetoresistive device. Non-selective chemical mechanical polishing removes any silicon nitride overlying a top electrode for the device along with silicon dioxide used for encapsulation. Later etching operations corresponding to formation of a via to reach the top electrode use selective etching chemistries that remove silicon dioxide to access the top electrode, but do not remove silicon nitride. Thus, the silicon nitride acts as an etch stop, and, in the resulting device, provides an insulating layer that prevents unwanted short circuits between the via and the bottom electrode and between the via and the sidewalls of the magnetoresistive device stack.Type: GrantFiled: August 29, 2016Date of Patent: August 8, 2017Assignee: EVERSPIN TECHNOLOGIES, INC.Inventors: Kerry Joseph Nagel, Sanjeev Aggarwal, Moazzem Hossain, Nicholas Rizzo
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Publication number: 20170117462Abstract: A method of manufacturing one or more interconnects to magnetoresistive structure comprising (i) depositing a first conductive material in a via; (2) etching the first conductive material wherein, after etching the first conductive material a portion of the first conductive material remains in the via, (3) partially filling the via by depositing a second conductive material in the via and directly on the first conductive material in the via; (4) depositing a first electrode material in the via and directly on the second conductive material in the via; (5) polishing a first surface of the first electrode material wherein, after polishing, the first electrode material is (i) on the second conductive material in the via and (ii) over the portion of the first conductive material remaining in the via; and (6) forming a magnetoresistive structure over the first electrode material.Type: ApplicationFiled: January 6, 2017Publication date: April 27, 2017Inventors: Kerry Joseph Nagel, Kenneth Smith, Moazzem Hossain, Sanjeev Aggarwal