Abstract: A user equipment (UE) tunes a transceiver of the UE to a first frequency associated with a first channel, transmits a first short packet to a second UE on the first channel and determines whether a first indication was received from the second UE in response to the first short packet. The first indication indicates that the first channel satisfies one or more predetermined criteria. The UE transmits then the primary data to the second UE on the first channel in response to the first indication being received from the second UE.

Abstract: A user equipment (UE) tunes a transceiver of the UE to a first frequency associated with a first channel, transmits a first short packet to a second UE on the first channel and determines whether a first indication was received from the second UE in response to the first short packet. The first indication indicates that the first channel satisfies one or more predetermined criteria. The UE transmits then the primary data to the second UE on the first channel in response to the first indication being received from the second UE.

Abstract: A method and system/circuit for multi-beamforming signal processing are provided. The circuit includes a plurality of basic modules associated with a plurality of transducers. Each basic module includes a first and second processing stages operative for introducing time delays of higher and lower temporal resolutions to the signals processed thereby respectively, and a path selector multiplexer module managing the signal coupling between the first and second stages. The first processing stage is connectable to one of the transducers via a first port and includes a network of first type time delay channels defining L signal paths operative at a relatively high sampling rate and adapted for providing L respectively different time delays of high temporal resolution. The second processing stage includes an array of N second type time delay channels operable for shifting signals processed thereby by any number up-to K samples of a lower sampling rate.

Abstract: Systems and methods are provided for utilizing ultra-efficiency low noise configurations for phased array antennas. Radio frequency integrated circuits (RFICs) may be used in phased array antennas to enable configuring large number of phase shifters in highly efficient manner, and to do so in optimal manner, such as with low noise.

Abstract: A method and system/circuit for multi-beamforming signal processing are provided. The circuit includes a plurality of basic modules associated with a plurality of transducers. Each basic module includes a first and second processing stages operative for introducing time delays of higher and lower temporal resolutions to the signals processed thereby respectively, and a path selector multiplexer module managing the signal coupling between the first and second stages. The first processing stage is connectable to one of the transducers via a first port and includes a network of first type time delay channels defining L signal paths operative at a relatively high sampling rate and adapted for providing L respectively different time delays of high temporal resolution. The second processing stage includes an array of N second type time delay channels operable for shifting signals processed thereby by any number up-to K samples of a lower sampling rate.

Abstract: A stacked synthesizer for wide local oscillator (LO) generation using a dynamic divider. The phase locked loop can include a plurality of voltage controlled oscillators (VCOs), and a selector that can be configured to select an output of one of the plurality of VCOs. The selected output of one of the plurality of VCOs can be provided to an on-chip dynamic divider and to an off-chip dynamic divider for LO sharing. The dynamic dividers can be configured to generate synthesizer outputs based on a multiplication of the selected output of one of the plurality of VCOs by a factor (1+1/M), where M is a variable number.

Abstract: Systems and methods are provided for utilizing ultra-efficiency low noise configurations for phased array antennas. Radio frequency integrated circuits (RFICs) may be used in phased array antennas to enable configuring large number of phase shifters in highly efficient manner, and to do so in optimal manner, such as with low noise.

Abstract: The present disclosure is directed to a modular and scalable front-end architecture for a massive MIMO communication device, such as a base station. The front-end architecture can allow for the number of antennas at the communication device to be increased or decreased in a simple and cost efficient manner. The front-end architecture can also allow for the number of data streams that can be transmitted and/or received by the communication device to be increased or decreased in a simple and cost efficient manner.

Abstract: A stacked synthesizer for wide local oscillator (LO) generation using a dynamic divider. The phase locked loop can include a plurality of voltage controlled oscillators (VCOs), and a selector that can be configured to select an output of one of the plurality of VCOs. The selected output of one of the plurality of VCOs can be provided to an on-chip dynamic divider and to an off-chip dynamic divider for LO sharing. The dynamic dividers can be configured to generate synthesizer outputs based on a multiplication of the selected output of one of the plurality of VCOs by a factor (1+1/M), where M is a variable number.

Abstract: A stacked synthesizer for wide local oscillator (LO) generation using a dynamic divider. The phase locked loop can include a plurality of voltage controlled oscillators (VCOs), and a selector that can be configured to select an output of one of the plurality of VCOs. The selected output of one of the plurality of VCOs can be provided to an on-chip dynamic divider and to an off-chip dynamic divider for LO sharing. The dynamic dividers can be configured to generate synthesizer outputs based on a multiplication of the selected output of one of the plurality of VCOs by a factor (1+1/M), where M is a variable number.

Abstract: A transceiver is disclosed which includes a transmitter and a receiver. The transmitter provides an impairment measurement signal, which is substantially similar to a transmitted communication signal except for a possible difference in phase and/or a magnitude, to the receiver. An envelope detector within the receiver provides an envelope of the impairment measurement signal to the transmitter. The transmitter determines sets of one or more filtering coefficients using the envelope of the impairment measurement signal and adjusts phases or magnitudes and/or phases of a sequences of bits used to generate the transmitted communication signal in accordance with the sets of one or more filtering coefficients to compensate for the unwanted distortion and/or the unwanted interference present within the transmitted communication signal.

Abstract: The present disclosure is directed to a modular and scalable front-end architecture for a massive MIMO communication device, such as a base station. The front-end architecture can allow for the number of antennas at the communication device to be increased or decreased in a simple and cost efficient manner. The front-end architecture can also allow for the number of data streams that can be transmitted and/or received by the communication device to be increased or decreased in a simple and cost efficient manner.

Abstract: A stacked synthesizer for wide local oscillator (LO) generation using a dynamic divider. The phase locked loop can include a plurality of voltage controlled oscillators (VCOs), and a selector that can be configured to select an output of one of the plurality of VCOs. The selected output of one of the plurality of VCOs can be provided to an on-chip dynamic divider and to an off-chip dynamic divider for LO sharing. The dynamic dividers can be configured to generate synthesizer outputs based on a multiplication of the selected output of one of the plurality of VCOs by a factor (1+1/M), where M is a variable number.

Abstract: A stacked synthesizer for wide local oscillator (LO) generation using a dynamic divider. The phase locked loop can include a plurality of voltage controlled oscillators (VCOs), and a selector that can be configured to select an output of one of the plurality of VCOs. The selected output of one of the plurality of VCOs can be provided to an on-chip dynamic divider and to an off-chip dynamic divider for LO sharing. The dynamic dividers can be configured to generate synthesizer outputs based on a multiplication of the selected output of one of the plurality of VCOs by a factor (1+1/M), where M is a variable number.

Abstract: A stacked synthesizer for wide local oscillator (LO) generation using a dynamic divider. The phase locked loop can include a plurality of voltage controlled oscillators (VCOs), and a selector that can be configured to select an output of one of the plurality of VCOs. The selected output of one of the plurality of VCOs can be provided to an on-chip dynamic divider and to an off-chip dynamic divider for LO sharing. The dynamic dividers can be configured to generate synthesizer outputs based on a multiplication of the selected output of one of the plurality of VCOs by a factor (1+1/M), where M is a variable number.