Abstract: The present invention provides a semiconductor memory device having a block write function to perform an image processing at a high speed for any region on an image plane. The semiconductor memory device comprises a column decoder circuit 1; a column address latch circuit 2; a write control circuit 3 including NMOS transistors 13; a column mask register 4 including registers 10; a color register 5 including registers 11n; a Y switch 6 including switches 14; a memory cell 7; a block write control circuit 8; a column mask control circuit 9 including NOR gates 12; a column address pre-decode circuit 15 corresponding to subordinate column addresses Y0, Y1 and Y2; and a column address pre-decode circuit 16 corresponding to superordinate column addresses Y3, Y4 and Y5.

Abstract: A column address selection circuit 1 is provided, which renders all column address signals (CSi), from a start address to a stop address designated by a column address signal (ADCd+ADCu), to be a selective level when a segment address selection signal (SASj) and a block write signal (BW) are at an active level. A segment address selection circuit 2 is provided, which renders all segment address selection signals (SASj), from the start address to the stop address designated by the column address signal (ADCu) of a superordinate side, to be a selection level to supply it to the column address selection circuit 1, when the block write signal (BW) is at the active level.