Abstract: A FIFO memory is disclosed which includes a plurality of memory cells, a mode circuit designating a first or a second mode in response to a mode signal supplied thereto, a selection circuit for selecting a first number of the memory cells each time a clock signal is generated in the first mode and for selecting a second number of the memory cells each time the clock signal is generated in the second mode, the first number being different from the second number, and an access circuit for accessing the selected memory cells to write data thereinto and to read data therefrom, whereby the number of memory cells to accessed is changeable in the mode to be performed.

Abstract: A semiconductor memory device having a serial access port and an improved redundant structure which can operate at a high speed is disclosed. The memory device comprises a normal memory cell array, a redundant memory cell array, a serial selection circuit for serially selecting data stored in the normal cell array in response to a control signal, a defective location memory for storing address of a defective memory cell or cells in the normal memory cell array, a counter incremented by the control signal for indicating the address selected by the serial selection circuit, a control circuit for selecting the redundant memory cell array when the content of the counter coincides with the content of the defective location memory, a plus-one circuit for generating an initial address which is larger than external initial address by one, and a count-up control circuit for applyig the control signal to the counter from its second occurrence after the application of the external initial address.

Abstract: A semiconductor memory circuit provided with an improved serial access circuit arrangement is disclosed. The memory circuit includes first and second memory arrays, a common data hold circuit, a first control circuit for enabling one of the first and second memory arrays, and a data transfer circuit which transfers data derived from the first memory array to the common data hold circuit when the first memory array is enabled and transfers data derived from the second memory array to the common data hold circuit when the second memory array is enabled.