Abstract: A control system and a method are disclosed for detecting and reporting a variety of faults in solar thermal systems. Detected and reported faults include a low fluid condition in a closed loop of a solar thermal system in a drain-back configuration, a pressure drop in a closed of a solar thermal system in a glycol configuration, a pressure drop in a potable water portion of a solar thermal system of either configuration. Additionally, systems and methods are disclosed for detecting and reporting power outages and heat exchanger scaling, both of which may be experienced by a solar thermal system.

Abstract: A method for generating consistent functional and timing definitions. The method includes providing a common source description, the common source description corresponding to multicycle paths in an integrated circuit chip design, transforming the common source description to a functional definition, monitoring a functional simulation of the integrated circuit chip design using the functional definition, transforming the common source description to a timing definition, and performing a timing analysis of the integrated circuit chip design using the timing definition.

Abstract: A method for generating consistent functional and timing definitions. The method includes providing a common source description, the common source description corresponding to multicycle paths in an integrated circuit chip design, transforming the common source description to a functional definition, monitoring a functional simulation of the integrated circuit chip design using the functional definition, transforming the common source description to a timing definition, and performing a timing analysis of the integrated circuit chip design using the timing definition.

Abstract: A microprocessor synchronously executes instructions, the instructions including integer instructions for performing integer operations and floating point instructions for performing real number operations. An instruction pipeline has a plurality of successive stages for synchronously executing each of the instructions in parallel, with integer and floating point instructions being intermixed in the pipeline. Each of the plurality of successive stages simultaneously operates on a different one of the instructions. An integer unit executes the integer instructions and forms an integer result based on an integer operation performed on at least one integer operand or integer result. A floating point unit executes the floating point instructions and forms a floating point result based on one such floating point operation performed on at least one floating point operand or floating point result.

Abstract: An embodiment of the present invention is a cache memory system for providing memory items staged from an, external memory to a logic unit. The system consists of a cache array comprising at least one single cache array structure wherein one such single cache array structure consists of a plurality of cache entries. Each of the cache entries consists of a memory item section for storing at least a portion of a memory item and a cache tag section for storing at least a portion of a cache tag. Each such cache tag identifies at least one of the cache entries. The cache array is responsive to address signals for reading out the contents of at least one of the cache entries. The system further consists of a logic circuit responsive to memory requests for generating the address signals and consists of a circuit for comparing the cache tags to the memory requests for a predetermined relationship.