Patents by Inventor Mohamad M. Mojaradi

Mohamad M. Mojaradi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5541439
    Abstract: There is disclosed a layout of a high voltage Darlington pair in which a circular field plate is utilized for both high voltage transistors in order to reduce the layout area. In this layout, both transistors of a Darlington pair are circular transistors and they both have a common center. This enables both high voltage transistors to share one field plate ring and one collector ring.
    Type: Grant
    Filed: November 17, 1994
    Date of Patent: July 30, 1996
    Assignee: Xerox Corporation
    Inventors: Mohamad M. Mojaradi, Guillermo Lao, Steven A. Buhler, Tuan A. Vo
  • Patent number: 5529046
    Abstract: The present invention is an apparatus for controlling the ignition of an internal combustion engine. The present invention employs a high voltage transistor, preferably a high voltage MOSFET, to switch DC voltages on the order of 1 kV to regulate the flow of current to an input tap of a primary ignition transformer or coil. The high voltage transistor is controllable by conventional logic-level voltages produced by an ignition control module.
    Type: Grant
    Filed: January 6, 1995
    Date of Patent: June 25, 1996
    Assignee: Xerox Corporation
    Inventors: John E. Werner, Alan J. Werner, Jr., Mohamad M. Mojaradi, Jerry F. Adams
  • Patent number: 5488301
    Abstract: An electrostatic voltmeter suitable for use in a non-contacting, positive or negative potential sensing, type electrostatic voltmeter. The invention enables a flexible, low cost electrostatic voltmeter to be produced using high-voltage field-effect transistors in the circuit design. The invention further includes input conditioning components that enable high-voltage sensing and high-voltage feedback in such a manner that processing of the input signal from the sensor is accomplished without producing a variation in the current passing through the field-effect transistor in response to voltage variations. Elimination of this variation further reduces the susceptibility of the remaining signal processing circuitry to transient direct current signals. A differential cascode as the input stage is the preferred configuration for the input conditioning components.
    Type: Grant
    Filed: December 19, 1994
    Date of Patent: January 30, 1996
    Assignee: Xerox Corporation
    Inventors: Alan J. Werner, Jr., Mohamad M. Mojaradi, Mehrdad Zomorrodi, Steven A. Buhler, Tuan A. Vo
  • Patent number: 5424226
    Abstract: A FET which can be formed on a silicon substrate and which can operate in the enhancement mode. The n+ source and drain are centrally located within n-wells which extend under the gate area, and are separated by a distance. By appropriately choosing the distance between n-wells, different threshold voltages can be obtained for several transistors on the same chip.
    Type: Grant
    Filed: April 11, 1994
    Date of Patent: June 13, 1995
    Assignee: Xerox Corporation
    Inventors: Tuan A. Vo, Mohamad M. Mojaradi, Guillermo Lao
  • Patent number: 5382826
    Abstract: A high current, high voltage transistor which can be easily electrically stacked to extend the voltage range and uses less silicon area than a conventional stacked transistor configuration and a configuration of field plates that provide the greatest breakdown voltages with the highest ohmic values. Also, a star shaped field plate design which provides the greatest breakdown voltages with the highest ohmic values. The field plate is constructed using several concentric rings connected by fingers that are wider at towards the center of the concentric rings and narrower towards the perimeter of the concentric rings.
    Type: Grant
    Filed: December 21, 1993
    Date of Patent: January 17, 1995
    Assignee: Xerox Corporation
    Inventors: Mohamad M. Mojaradi, Tuan A. Vo
  • Patent number: 5381018
    Abstract: A variable impedance circuit in which an optoisolator transistor is controlled by an input light emitting diode to turn on a series of high voltage MOSFETs for use in applications currently using light emitting diode controlled with a light dependent resistor.
    Type: Grant
    Filed: December 20, 1993
    Date of Patent: January 10, 1995
    Assignee: Xerox Corporation
    Inventors: Mohamad M. Mojaradi, Tuan A. Vo
  • Patent number: 5357393
    Abstract: An integrated high voltage device with an ultra low leakage input protection circuit to be used in highly sensitive circuits which require ultra low input leakage current. The protection circuit has a common substrate with the integrated circuit device and the common substrate is floating. The floating substrate provides a way of designing a protection circuit with small diodes which have ultra low input D.C. leakage. The protection circuit includes a resistor and two small Zener diodes which can clamp and protect the device during normal operating conditions up to voltages such as 1700 volts.
    Type: Grant
    Filed: May 5, 1992
    Date of Patent: October 18, 1994
    Assignee: Xerox Corporation
    Inventors: Mohamad M. Mojaradi, Guillermo Lao, Dale Sumida
  • Patent number: 5349223
    Abstract: A vertical transistor which is built in a substrate of a given first carrier type utilizing standard processes but which has a unique layout which facilitates high voltage, high current operation while still conserving space. The transistor is built utilizing a repeatable combination gate/source area that is built in the upper area of the substrate such that the remaining lower portion of the substrate underneath the combination gate/source area is the drain area of the transistor.
    Type: Grant
    Filed: December 14, 1993
    Date of Patent: September 20, 1994
    Assignee: Xerox Corporation
    Inventors: Mohamad M. Mojaradi, Tuan A. Vo, Steven A. Buhler
  • Patent number: 5329147
    Abstract: When a field effect transistor is used to control the current through an inductive load, the flyback voltage is felt through the vertical pnp transistor at the drain, which onducts to the substrate. This current represents a power loss and a source of heat. This invention supplies a second lateral transistor which conducts this current back to the power supply.
    Type: Grant
    Filed: January 4, 1993
    Date of Patent: July 12, 1994
    Assignee: Xerox Corporation
    Inventors: Tuan A. Vo, Mohamad M. Mojaradi, Aram Nahidipour
  • Patent number: 5328859
    Abstract: A high voltage bipolar transistor fabricated on a CMOS substrate without adding any additional process steps. During the CMOS n-well mask and implant steps an n-well is formed for the transistor. Next, during the CMOS field and deep boron implant steps a circular p-field is formed within the n-well. Finally, during the CMOS p+ mask and implant steps the p+ emitter is formed. The presence of the p-field between the emitter and n+ base provides high voltage protection.
    Type: Grant
    Filed: January 4, 1993
    Date of Patent: July 12, 1994
    Assignee: Xerox Corporation
    Inventors: Tuan A. Vo, Mohamad M. Mojaradi
  • Patent number: 5321293
    Abstract: A semiconductor circuit integrated with CMOS circuits for receiving a TTL input voltage and generating a large negative and positive voltage swing with respect to p-type or n-type substrate is disclosed. This invention is based on elimination of the electro-static discharge (ESD) protection circuit which is a requirement for any integrated circuit. Eliminating the ESD protection circuit also eliminates the clamping feature of the ESD protection circuit and therefore the circuit can be driven to negative voltages for PMOS circuits and to positive voltages for NMOS circuits. This provides the possibility of connecting the drain of a a P-channel type metal oxide silicon field effect (PMOS) transistor, which is fabricated on a p-type substrate within an n-well, to a voltage below the the substrate voltage. Also, in a n-channel type metal oxide silicon field effect (NMOS) transistor which is fabricated on a n-type substrate within a P-well, the drain can be connected to voltages higher than the substrate voltage.
    Type: Grant
    Filed: July 12, 1993
    Date of Patent: June 14, 1994
    Assignee: Xerox Corporation
    Inventors: Mohamad M. Mojaradi, Tuan Vo, Jaime Lerma, Steven A. Buhler
  • Patent number: 5270660
    Abstract: An electrostatic measurement apparatus for generating a modified electrical signal in proportion to an electrostatic potential present on a surface. The apparatus includes a sensor for producing a signal representative of the electrostatic potential on the surface. The apparatus also includes high-voltage and low-voltage devices combined to produce an amplifier which transforms the sensor signal into a low-voltage signal indicative the surface potential. The electrostatic measurement apparatus is implemented using high-voltage and low-voltage integrated circuit technology.
    Type: Grant
    Filed: May 5, 1992
    Date of Patent: December 14, 1993
    Assignee: Xerox Corporation
    Inventors: Alan J. Werner, Jr., Mohamad M. Mojaradi, Guillermo Lao, Dale Sumida, Mostafa R. Yazdy, Harry J. McIntyre, Mehrdad Zomorrodi
  • Patent number: 5229308
    Abstract: A method of manufacturing a semiconductor device having a bipolar transistor for ordinary logic operation, as well as a high voltage MOS transistor which are provided in a single semiconductor substrate. The process includes the steps of making high voltage MOS transistors which comprises the steps of n-well fabrication, first drift region fabrication, second drift region fabrication, source and drain contact region fabrication and making bipolar transistors within the same silicon substrate as the high voltage MOS transistors which includes the step of base region fabrication where the steps for fabricating the second drift region of the high voltage MOS transistor and the base region of the bipolar transistor are combined so that both regions are created simultaneously.
    Type: Grant
    Filed: May 4, 1992
    Date of Patent: July 20, 1993
    Assignee: Xerox Corporation
    Inventors: Tuan A. Vo, Mohamad M. Mojaradi, Steven A. Buhler