Patents by Inventor Mohamed A. Abdelsalam
Mohamed A. Abdelsalam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240141780Abstract: Some examples described herein relate to producing an optimized composition of a downhole drilling fluid. For example, a system can execute an iterative optimization process to determine an optimized composition of downhole drilling fluid that satisfies at least one objective function and matches a received set of target fluid properties. Each iteration of the iterative optimization process can involve: selecting a mixture of fluid components for the downhole drilling fluid from a search space, providing the selected mixture of fluid components as input to a trained machine-learning model, receiving a set of predicted fluid properties for the mixture of fluid components as output from the trained machine-learning model, and determining whether the set of predicted fluid properties matches the set of target fluid properties. The system can transmit a control signal to a mixing subsystem for causing the mixing subsystem to produce the optimized composition of the downhole drilling fluid.Type: ApplicationFiled: November 2, 2022Publication date: May 2, 2024Inventors: Feng Feng, Fahad Ahmad, Tywon C. Veazie, Jason Glen Bell, Jay Deville, Mohamed Abdelsalam
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Publication number: 20230261373Abstract: Aspects of this disclosure relate to an array calibration system and method using probes disposed between antenna elements. In certain embodiments, the calibration is performed by measuring near-field relative phase and amplitude measurements of the antenna elements and using such relative measurements to adjust the amplitude and phase of the transceivers connected to the antenna elements. In some embodiments, each antenna element within a set of antenna elements transmits a signal that is received by a single probe, and the received signals are assessed to determine relative phase or amplitude measurements. In some embodiments, a single probe transmits a signal that is received by each antenna element within a set of antenna elements, and the received signals are assessed to determine relative phase and amplitude measurements.Type: ApplicationFiled: April 19, 2023Publication date: August 17, 2023Inventors: Ahmed I. Khalil, Mohamed A. Abdelsalam
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Patent number: 11295828Abstract: Systems and methods for multi-chip programming for phased arrays are provided herein. In certain embodiments, a semiconductor device includes one or more inputs configured to receive frame data, an internal memory configured to store the received frame data, and a shift register configured to receive the frame data and comprising a plurality of shift register bit positions. The device further includes a latch configured to store a command type, a first multiplexor configured to select at least one first bit from the shift register based on the command type and provide the at least one first bit to the latch, an output configured to output the frame data, and a second multiplexor configured to select at least one second bit from the shift register based on the command type and provide the at least one second bit to the output.Type: GrantFiled: February 13, 2020Date of Patent: April 5, 2022Assignee: Analog Devices International Unlimited CompanyInventors: Stuart John McCracken, Mohamed El-Nozahi, Mohamed Abdelsalam
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Patent number: 11101782Abstract: Polyphase filters (PPFs) can be used to generate quadrature or other phase-shifted representations of an input signal provided to the PPF. In one approach, a “passive” polyphase filter can include a combination of resistive and capacitive elements. Such a topology can be referred to as an RC-PPF topology. Another passive circuit topology can be used to provide a PPF, by replacing the resistive elements with inductive elements, and by replacing the capacitive elements with resistive elements. A filter circuit can include cascaded RC-PPF and LR-PPF sections, such as in an alternating manner (e.g., an “RC-LR” topology). In this approach, a total insertion loss of cascaded LR-PPF and RC-PPF sections can be reduced as compared to using LR-PPF or RC-PPF sections, alone.Type: GrantFiled: July 16, 2019Date of Patent: August 24, 2021Assignee: Analog Devices International Unlimited CompanyInventors: Mohamed Abdelsalam, Hesham Beshary, Mohamed A. Abdalla
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Publication number: 20200286571Abstract: Systems and methods for multi-chip programming for phased arrays are provided herein. In certain embodiments, a semiconductor device includes one or more inputs configured to receive frame data, an internal memory configured to store the received frame data, and a shift register configured to receive the frame data and comprising a plurality of shift register bit positions. The device further includes a latch configured to store a command type, a first multiplexor configured to select at least one first bit from the shift register based on the command type and provide the at least one first bit to the latch, an output configured to output the frame data, and a second multiplexor configured to select at least one second bit from the shift register based on the command type and provide the at least one second bit to the output.Type: ApplicationFiled: February 13, 2020Publication date: September 10, 2020Inventors: Stuart John McCracken, Mohamed El-Nozahi, Mohamed Abdelsalam
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Patent number: 10707878Abstract: Described herein is apparatus and system for a digitally controlled oscillator (DCO). The apparatus comprises a voltage regulator to provide an adjustable power supply; and a DCO to generate an output clock signal, the DCO including one or more delay elements, each delay element operable to change its propagation delay via the adjustable power supply, wherein each delay element comprising an inverter with adjustable drive strength, wherein the inverter is powered by the adjustable power supply. The apparatus further comprises a digital controller to generate a first signal for instructing the voltage regulator to adjust a voltage level of the adjustable power supply.Type: GrantFiled: August 20, 2015Date of Patent: July 7, 2020Assignee: Intel CorporationInventors: Amr M. Lotfy, Mohamed A. Abdelsalam, Mohammed W. El Mahalawy, Nasser A. Kurd, Mohamed A. Abdelmoneum
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Patent number: 10678976Abstract: Aspects of the disclosed technology relate to techniques for protocol analysis during a circuit design verification process. A protocol-specific message capture unit captures messages while or after being transmitted over one or more communication channels between a circuit design model and one or more target devices. A protocol-independent interface unit receives signals carrying the messages and information for processing the messages from the protocol-specific message capture unit. After processing the messages, the protocol-independent interface unit sends the messages to an analysis unit for analyzing the messages based on a protocol file. The analysis unit may then output the messages for displaying.Type: GrantFiled: January 17, 2018Date of Patent: June 9, 2020Assignee: Mentor Graphics CorporationInventors: Mahmoud Mohamed Ali, Mohamed Abdelsalam Ahmed Hassan, Ashraf Mohamed Salem, Robert John Bloor
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Publication number: 20180300440Abstract: Aspects of the disclosed technology relate to techniques for protocol analysis during a circuit design verification process. A protocol-specific message capture unit captures messages while or after being transmitted over one or more communication channels between a circuit design model and one or more target devices. A protocol-independent interface unit receives signals carrying the messages and information for processing the messages from the protocol-specific message capture unit. After processing the messages, the protocol-independent interface unit sends the messages to an analysis unit for analyzing the messages based on a protocol file. The analysis unit may then output the messages for displaying.Type: ApplicationFiled: January 17, 2018Publication date: October 18, 2018Inventors: Mahmoud Mohamed Ali, Mohamed Abdelsalam Ahmed Hassan, Ashraf Mohamed Salem, Robert John Bloor
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Patent number: 10020931Abstract: Described is an integrated circuit (IC) with apparatus for dynamically adapting a clock generator, e.g., phase locked loop (PLL), with respect to changes in power supply. The apparatus comprises: a voltage droop detector coupled to power supply node, the voltage droop detector to generate a digital code word representing voltage droop on the power supply node; and a PLL including a ring oscillator coupled to the power supply node, the ring oscillator to generate an output clock signal, the ring oscillator operable to adjust frequency of the output clock signal according to the digital code word.Type: GrantFiled: March 7, 2013Date of Patent: July 10, 2018Assignee: Intel CorporationInventors: Mohamed A. Abdelmoneum, Nasser A. Kurd, Amr M. Lotfy, Mamdouh O. Abd El-Mejeed, Mohamed A. Abdelsalam
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Publication number: 20180097817Abstract: Securely storing assets in a cloud computer storage service. Preparation to store assets for a user may comprise determining a location to store the assets, generating a write access signature, and sending the determined location and the signature to the user. A request is received from the user to store the assets. Such a request includes the assets, the location, and the signature. In response to receiving the request, a determination is made regarding the write access signature whether the request should be honored. When the request is honored, the assets are stored in the determined location and the write access signature is invalidated. Upon subsequent user requests to access the assets, short-term read access signatures are generated and provided to the user. The assets are written once per generated write access signature and reads are to be performed close in time to when short-term read access signatures are requested.Type: ApplicationFiled: September 30, 2016Publication date: April 5, 2018Inventors: Mohamed Abdelsalam Noureldien Aboubakr, Samuel Lenz Banina, Kyle Anthony Werner, David James Messner, Rajasekaran Rangarajan, Andrew Michael Pennell, Mariyan D. Fransazov
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Publication number: 20180062260Abstract: Aspects of this disclosure relate to an array calibration system and method using probes disposed between antenna elements. In certain embodiments, the calibration is performed by measuring near-field relative phase and amplitude measurements of the antenna elements and using such relative measurements to adjust the amplitude and phase of the transceivers connected to the antenna elements. In some embodiments, each antenna element within a set of antenna elements transmits a signal that is received by a single probe, and the received signals are assessed to determine relative phase or amplitude measurements. In some embodiments, a single probe transmits a signal that is received by each antenna element within a set of antenna elements, and the received signals are assessed to determine relative phase and amplitude measurements.Type: ApplicationFiled: June 1, 2017Publication date: March 1, 2018Inventors: Ahmed I. Khalil, Mohamed A. Abdelsalam
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Patent number: 9628094Abstract: Described is an integrated circuit (IC) with a phase locked loop with capability of fast locking. The IC comprises: a node to provide a reference clock; a digitally controlled oscillator (DCO) to generate an output clock; a divider coupled to the DCO, the divider to divide the output clock and to generate a feedback clock; and control logic operable to reset the DCO and the divider, and operable to release reset in synchronization with the reference clock. An apparatus for zeroing phase error is provided which comprises a first node to provide a reference clock; a second node to provide a feedback clock; a time-to-digital converter, coupled to the first and second nodes, to measure phase error between the reference and feedback clocks; a digital loop filter; and a control unit to adjust the measured phase error, and to provide the adjusted phase error to the digital loop filter.Type: GrantFiled: September 26, 2013Date of Patent: April 18, 2017Assignee: Intel CorporationInventors: Amr M. Lotfy, Mohamed A. Abdelsalam, Mamdouh O. Abd El-Mejeed, Nasser A. Kurd, Mohamed A. Abdelmoneum, Mark Elzinga, Young Min Park, Jagannadha R. Rapeta, Surya Musunuri
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Publication number: 20160204787Abstract: Described is an integrated circuit (IC) with a phase locked loop with capability of fast locking. The IC comprises: a node to provide a reference clock; a digitally controlled oscillator (DCO) to generate an output clock; a divider coupled to the DCO, the divider to divide the output clock and to generate a feedback clock; and control logic operable to reset the DCO and the divider, and operable to release reset in synchronization with the reference clock. An apparatus for zeroing phase error is provided which comprises a first node to provide a reference clock; a second node to provide a feedback clock; a time-to-digital converter, coupled to the first and second nodes, to measure phase error between the reference and feedback clocks; a digital loop filter; and a control unit to adjust the measured phase error, and to provide the adjusted phase error to the digital loop filter.Type: ApplicationFiled: September 26, 2013Publication date: July 14, 2016Inventors: Amr M. LOTFY, Mohamed A. ABDELSALAM, Mamdouh O. ABD EL-MEJEED, Nasser A. KURD, Mohamed A. ABDELMONEUM, Mark ELZINGA, Young Min PARK, Jagannadha R. RAPETA, Surya MUSUNURI
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Patent number: 9257994Abstract: Described herein is apparatus and system for a digitally controlled oscillator (DCO). The apparatus comprises a voltage regulator to provide an adjustable power supply; and a DCO to generate an output clock signal, the DCO including one or more delay elements, each delay element operable to change its propagation delay via the adjustable power supply, wherein each delay element comprising an inverter with adjustable drive strength, wherein the inverter is powered by the adjustable power supply. The apparatus further comprises a digital controller to generate a first signal for instructing the voltage regulator to adjust a voltage level of the adjustable power supply.Type: GrantFiled: March 22, 2012Date of Patent: February 9, 2016Inventors: Amr M. Lotfy, Mohamed A. Abdelsalam, Mohammed W. El Mahalawy, Nasser A. Kurd, Mohamed A. Abdelmoneum
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Publication number: 20160006443Abstract: Described herein is apparatus and system for a digitally controlled oscillator (DCO). The apparatus comprises a voltage regulator to provide an adjustable power supply; and a DCO to generate an output clock signal, the DCO including one or more delay elements, each delay element operable to change its propagation delay via the adjustable power supply, wherein each delay element comprising an inverter with adjustable drive strength, wherein the inverter is powered by the adjustable power supply. The apparatus further comprises a digital controller to generate a first signal for instructing the voltage regulator to adjust a voltage level of the adjustable power supply.Type: ApplicationFiled: August 20, 2015Publication date: January 7, 2016Inventors: Amr M. LOTFY, Mohamed A. ABDELSALAM, Mohammed W. EL MAHALAWY, Nasser A. KURD, Mohamed A. ABDELMONEUM
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Publication number: 20140254734Abstract: Described is an integrated circuit (IC) with apparatus for dynamically adapting a clock generator, e.g., phase locked loop (PLL), with respect to changes in power supply. The apparatus comprises: a voltage droop detector coupled to power supply node, the voltage droop detector to generate a digital code word representing voltage droop on the power supply node; and a PLL including a ring oscillator coupled to the power supply node, the ring oscillator to generate an output clock signal, the ring oscillator operable to adjust frequency of the output clock signal according to the digital code word.Type: ApplicationFiled: March 7, 2013Publication date: September 11, 2014Inventors: Mohamed A. Abdelmoneum, Nasser A. Kurd, Amr M. Lotfy, Mamdouh O. Abd El-Mejeed, Mohamed A. Abdelsalam
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Publication number: 20130307631Abstract: Described herein is apparatus and system for a digitally controlled oscillator (DCO). The apparatus comprises a voltage regulator to provide an adjustable power supply; and a DCO to generate an output clock signal, the DCO including one or more delay elements, each delay element operable to change its propagation delay via the adjustable power supply, wherein each delay element comprising an inverter with adjustable drive strength, wherein the inverter is powered by the adjustable power supply. The apparatus further comprises a digital controller to generate a first signal for instructing the voltage regulator to adjust a voltage level of the adjustable power supply.Type: ApplicationFiled: March 22, 2012Publication date: November 21, 2013Inventors: Amr M. Lotfy, Mohamed A. Abdelsalam, Mohammed W. El Mahalawy, Nasser A. Kurd, Mohamed A. Abdelmoneum