Abstract: A load detection circuit includes a variable current source circuit having a first input connected to a power supply, a second input, and a first output connected to an output load; a switched capacitor circuit having a third input connected to an external voltage reference signal, a fourth input connected to the first output of the variable current source, a fifth input connected to ground, a sixth input, and a second output; a comparator having a seventh input connected to the second output of the switched capacitor circuit, an eighth input connected to the first output of the variable current source, and a third output; an edge detector having a ninth input connected to the third output of the comparator, and a fourth output; and a digital controller having a fifth output connected to the variable current source and a sixth output connected to the switched capacitor circuit.

Abstract: A novel low power enable circuit is less sensitive to power supply variations while consuming less than 50 nA of supply current. The enable circuit includes a voltage clamp circuit which limits the supply level for a first inverter. The clamp circuit having a first input connected to a supply, a second input connected to chip enable, and a first output.

Abstract: A load detection circuit includes a variable current source circuit having a first input connected to a power supply, a second input, and a first output connected to an output load; a switched capacitor circuit having a third input connected to an external voltage reference signal, a fourth input connected to the first output of the variable current source, a fifth input connected to ground, a sixth input, and a second output; a comparator having a seventh input connected to the second output of the switched capacitor circuit, an eighth input connected to the first output of the variable current source, and a third output; an edge detector having a ninth input connected to the third output of the comparator, and a fourth output; and a digital controller having a fifth output connected to the variable current source and a sixth output connected to the switched capacitor circuit.

Abstract: A reference generation circuit includes a reference circuit and a local supply regulation circuit connected between an input supply and the reference circuit to supply a local regulated input to the reference circuit. The local supply regulation circuit comprises an error amplifier and a pass device, and wherein the error amplifier senses an output voltage of the pass device and an output voltage of the reference generation circuit to generate an output to control a gate terminal of the pass device.

Abstract: A method to adjust the load transient regulation of a low drop-out (LDO)/load switch linear voltage regulator (LVR) with an n-type pass element having an open loop transfer function, including determining during a load transient event if the gate of the pass—element goes lower than a scaled value of the output voltage or a constant voltage level, generating a control signal that controls a current sink block if the gate voltage of the pass element is lower than the output voltage, and enabling a current sink block that is controlled by the control signal and connecting the output of the current sink block to the output of the LVR.

Abstract: A novel low power enable circuit is less sensitive to power supply variations while consuming less than 50 nA of supply current. The enable circuit includes a voltage clamp circuit which limits the supply level for a first inverter. The clamp circuit having a first input connected to a supply, a second input connected to chip enable, and a first output.

Abstract: A low drop-out (LDO)/load switch linear voltage regulator (LVR) circuit having a first input terminal and a first output terminal, includes: a passive network with a second input terminal connected to the first input terminal and a second output terminal; a feedback network with a third input terminal connected to the first output terminal and a third output terminal; a pass element having a fourth input terminal connected to the first input terminal, a fourth output terminal connected to the first output terminal and first control terminal; a combiner having a fifth input connected to the second input, a sixth input connected to the third output and a fifth output connected to the first control terminal.

Abstract: An architecture and method to maintain stability of a low drop-out (LDO)/load switch linear voltage regulator (LVR). The architecture method support optionally determining during a power-up phase and by using a load detection circuit, the estimated load parameters that represents at least one selected from a group consisting of: the load time constant and the load resistor at an output node of the LDO/load switch LVR, and adjusting, based on the estimated output load parameters, an adaptive RC network in the LDO/load switch LVR, wherein the adaptive RC network produces an adaptive zero in a feedback network transfer function of the LDO/load switch LVR, wherein the adaptive zero reduces an effect of a non-dominant pole in the open loop transfer function of the LDO/load switch LVR, and wherein a frequency of the adaptive zero is adjusted based on the estimated load parameters.

Abstract: Inrush current is a critical, undesirable behavior that results from the uncontrolled start-up or shut-down of voltage regulators. Large inrush currents lead to voltage overshoot at the output node of voltage regulators and this can damage the regulator load, in addition to peak current that can damage the packaging or the regulator itself. Embodiments of the invention introduce methods of inrush current reduction based on voltage reference generation. For example, one method is based on multiple filtered steps of the voltage reference for the voltage regulator. For example, another method is based on creating a voltage reference signal that has a continuous slope starting from zero and ending at zero. Embodiments of the invention reduce or limit the inrush current for sensitive applications.

Abstract: A low drop-out (LDO)/load switch linear voltage regulator (LVR) circuit having a first input terminal and a first output terminal, includes: a passive network with a second input terminal connected to the first input terminal and a second output terminal; a feedback network with a third input terminal connected to the first output terminal and a third output terminal; a pass element having a fourth input terminal connected to the first input terminal, a fourth output terminal connected to the first output terminal and first control terminal; a combiner having a fifth input connected to the second input, a sixth input connected to the third output and a fifth output connected to the first control terminal.

Abstract: A method to adjust the load transient regulation of a low drop-out (LDO)/load switch linear voltage regulator (LVR) with an n-type pass element having an open loop transfer function, including determining during a load transient event if the gate of the pass—element goes lower than a scaled value of the output voltage or a constant voltage level, generating a control signal that controls a current sink block if the gate voltage of the pass element is lower than the output voltage, and enabling a current sink block that is controlled by the control signal and connecting the output of the current sink block to the output of the LVR.

Abstract: An architecture and method to maintain stability of a low drop-out (LDO)/load switch linear voltage regulator (LVR). The architecture method support optionally determining during a power-up phase and by using a load detection circuit, the estimated load parameters that represents at least one selected from a group consisting of: the load time constant and the load resistor at an output node of the LDO/load switch LVR, and adjusting, based on the estimated output load parameters, an adaptive RC network in the LDO/load switch LVR, wherein the adaptive RC network produces an adaptive zero in a feedback network transfer function of the LDO/load switch LVR, wherein the adaptive zero reduces an effect of a non-dominant pole in the open loop transfer function of the LDO/load switch LVR, and wherein a frequency of the adaptive zero is adjusted based on the estimated load parameters.

Abstract: A method to maintain stability of a low drop-out (LDO)/load switch linear voltage regulator (LVR). The method includes determining, during a power-up phase and by a capacitance sensing circuit, an estimated output capacitance value at an output node of the LDO/load switch LVR, and adjusting, based on the estimated output capacitance value, an adaptive RC network in the LDO/load switch LVR, wherein the adaptive RC network produces an adaptive zero in a feedback network transfer function of the LDO/load switch LVR, wherein the adaptive zero reduces an effect of a non-dominant pole in the open loop transfer function of the LDO/load switch LVR, and wherein a frequency of the adaptive zero is inversely proportional to the estimated output capacitance value.

Abstract: A method to maintain stability of a low drop-out (LDO)/load switch linear voltage regulator (LVR). The method includes determining, during a power-up phase and by a capacitance sensing circuit, an estimated output capacitance value at an output node of the LDO/load switch LVR, and adjusting, based on the estimated output capacitance value, an adaptive RC network in the LDO/load switch LVR, wherein the adaptive RC network produces an adaptive zero in a feedback network transfer function of the LDO/load switch LVR, wherein the adaptive zero reduces an effect of a non-dominant pole in the open loop transfer function of the LDO/load switch LVR, and wherein a frequency of the adaptive zero is inversely proportional to the estimated output capacitance value.

Abstract: A novel architecture and method to maintain stability of a low drop-out (LDO)/load switch linear voltage regulator (LVR). The architecture and method also support optionally determining, during a power-up phase and by a capacitance sensing circuit, an estimated output capacitance value at an output node of the LDO/load switch LVR, and adjusting, based on the estimated output capacitance value, an adaptive RC network in the LDO/load switch LVR, wherein the adaptive RC network produces an adaptive zero in a feedback network transfer function of the LDO/load switch LVR, wherein the adaptive zero reduces an effect of a non-dominant pole in the open loop transfer function of the LDO/load switch LVR, and wherein a frequency of the adaptive zero is inversely proportional to the estimated output capacitance value.

Abstract: A method to maintain stability of a low drop-out linear voltage regulator (LDO) includes sensing, by a voltage controlled variable resistor, a node voltage in a feedback network of the LDO linear voltage regulator, wherein the feedback network includes an error amplifier configured to regulate an output voltage level of the LDO based on a reference voltage, wherein the node voltage has a dependency on a resistive load current of the LDO, and adjusting, by the voltage controlled variable resistor and based on the sensed node voltage, a resistance value of a RC network in the feedback network, wherein the adaptive RC network produces an adaptive zero in a transfer function of the feedback network, wherein the adaptive zero reduces phase margin degradation due to an output non-dominant pole in the transfer function, and wherein a frequency of the adaptive zero is inversely proportional to the resistance value.

Abstract: A method to maintain stability of a low drop-out linear voltage regulator (LDO). The method includes sensing, by a voltage controlled variable resistor, a node voltage in a feedback network of the LDO linear voltage regulator, wherein the feedback network comprises an error amplifier configured to regulate an output voltage level of the LDO based on a reference voltage, wherein the node voltage has a dependency on a resistive load current of the LDO, and adjusting, by the voltage controlled variable resistor and based on the sensed node voltage, a resistance value of a RC network in the feedback network, wherein the adaptive RC network produces an adaptive zero in a transfer function of the feedback network, wherein the adaptive zero reduces phase margin degradation due to an output non-dominant pole in the transfer function, and wherein a frequency of the adaptive zero is inversely proportional to the resistance value.