Abstract: Disclosed are techniques for detecting hotspots using parameter matching. According to various implementations of the invention, devices in an electronic circuit design are classified into device groups based on their values for one or more device parameters, which can be derived from layout data describing the devices. Representative electrical information for each of the device groups is determined and used as a basis for hotspot detection.

Abstract: Disclosed are techniques for detecting hotspots using parameter matching. According to various implementations of the invention, devices in an electronic circuit design are classified into device groups based on their values for one or more device parameters, which can be derived from layout data describing the devices. Representative electrical information for each of the device groups is determined and used as a basis for hotspot detection.

Abstract: The length of an optical simulation site for an edge fragment may be determined based on the maximum and minimum intensity locations near the edge fragment. The width/space centerline's location may be used to approximate the minimum/maximum intensity location. The methods help reduce the optical proximity correction runtime without sacrificing the optical proximity correction output quality.

Abstract: Various implementations of the present invention provide a method of determining is a optical proximity correction process model sufficiently covered the layout design. More particularly, various implementations of the invention provide a method for interpolating between test pattern features relative to layout design features under test.

Abstract: A system and method for determining whether a desired integrated circuit layout can be accurately modeled from a resist model that is calibrated from a mask test pattern. In one embodiment, a chessboard graph is created having horizontal and vertical axes that are assigned two imaging parameters calculated from the test mask data and the desired integrated circuit layout data. Data on the horizontal and vertical axes of the chessboard graph are divided into a number of ranges or bins. The intersection of each bin on the horizontal and vertical axis is associated with a subgraph that plots the relation between two additional imaging parameters having values of the first two imaging parameters in the ranges of the intersecting bin.

Abstract: A system and method for determining whether a desired integrated circuit layout can be accurately modeled from a resist model that is calibrated from a mask test pattern. In one embodiment, a chessboard graph is created having horizontal and vertical axes that are assigned two imaging parameters calculated from the test mask data and the desired integrated circuit layout data. Data on the horizontal and vertical axes of the chessboard graph are divided into a number of ranges or bins. The intersection of each bin on the horizontal and vertical axis is associated with a subgraph that plots the relation between two additional imaging parameters having values of the first two imaging parameters in the ranges of the intersecting bin.