Abstract: A summary of a text document may be presented in the form of a list of points. A summary of text can be created by choosing words or groups of words from the original text, by modifying words in the original text, etc. Collections of the chosen words can be presented in a list form together with a mark that indicates that the text is a list of words that might not form complete sentences. Presentation of a summary in list form may lower a reader's expectation as to readability issues such as sentence flow, word flow, etc., and thus the reader may be more accepting of a machine-generated summary presented in list form than of a machine generated summary presented as sentences or paragraphs.

Abstract: A method for making one or more digital documents browseable. In one implementation, the digital documents may be automatically, topically segmented into one or more topical segments. A topical segment may be selected from the topical segments. One or more topical segments that are substantially similar to the selected topical segment may be identified. One or more links between the selected topical segment and the identified topical segment may be established. The established links may be displayed.

Abstract: According to the present invention, semiconductor device breakdown voltage can be increased by embedding field shaping regions within a drift region of the semiconductor device. A controllable current path extends between two device terminals on the top surface of a planar substrate, and the controllable current path includes the drift region. Each field shaping region includes two or more electrically conductive regions that are electrically insulated from each other, and which are capacitively coupled to each other to form a voltage divider dividing a potential between the first and second terminals. One or more of the electrically conductive regions are isolated from any external electrical contact. Such field shaping regions can provide enhanced electric field uniformity in current-carrying parts of the drift region, thereby increasing device breakdown voltage.

Abstract: A trench MIS device includes a thick dielectric layer at the bottom of the trench. The thick dielectric layer can be formed by the deposition or thermal growth of a dielectric material, such as silicon dioxide, on the bottom portion of the trench. The thick dielectric layer, which reduces the capacitance between the drain and gate of the device, can be formed in both the active areas of the device, where the switching function is performed, and in the inactive areas where, among other things, contacts are made to the gate electrode.

Abstract: A trench MOSFET is formed in a structure which includes a P-type epitaxial layer overlying an N+ substrate. A trench is formed in the epitaxial layer. A drain-drift region is formed by implanting N-type dopant through the bottom of the trench at different energies, creating a stack of N-type regions that extend from the bottom of the trench to the substrate. The energy and implant dose of the regions are set such that doping concentration of the drain-drift region increases monotonically with increasing depth below the bottom of the trench.

Abstract: A trench MIS device is formed in a P-epitaxial layer that overlies an N-epitaxial layer and an N+ substrate. In one embodiment, the device includes an N-type drain-drift region that extends from the bottom of the trench to the N-epitaxial layer. Preferably, the drain-drift region is formed at least in part by fabricating spacers on the sidewalls of the trench and implanting an N-type dopant between the sidewall spacers and through the bottom of the trench. The drain-drift region can be doped more heavily than the conventional “drift region” that is formed in an N-epitaxial layer. Thus, the device has a low on-resistance. The device can be terminated by a plurality of polysilicon-filled termination trenches located near the edge of the die, with the polysilicon in each termination trench being connected to the mesa adjacent the termination trench. The polysilicon material in each termination trenches.

Abstract: A trench MIS device is formed in a P-epitaxial layer that overlies an N-epitaxial layer and an N+ substrate. In one embodiment, the device includes an N-type drain-drift region that extends from the bottom of the trench to the N-epitaxial layer. Preferably, the drain-drift region is formed at least in part by fabricating spacers on the sidewalls of the trench and implanting an N-type dopant between the sidewall spacers and through the bottom of the trench. The drain-drift region can be doped more heavily than the conventional “drift region” that is formed in an N-epitaxial layer. Thus, the device has a low on-resistance. The device can be terminated by a plurality of polysilicon-filled termination trenches located near the edge of the die, with the polysilicon in each termination trench being connected to the mesa adjacent the termination trench. The polysilicon material in each termination trenches.

Abstract: A trench MIS device is formed in a P-epitaxial layer that overlies an N+ substrate. In one embodiment, the device includes a thick oxide layer at the bottom of the trench and an N-type drain-drift region that extends from the bottom of the trench to the substrate. The thick insulating layer reduces the capacitance between the gate and the drain and therefore improves the ability of the device to operate at high frequencies. Preferably, the drain-drift region is formed at least in part by fabricating spacers on the sidewalls of the trench and implanting an N-type dopant between the sidewall spacers and through the bottom of the trench. The thick bottom oxide layer is formed on the bottom of the trench while the sidewall spacers are still in place. Therefore, in embodiments where the thermal budget of the process is limited following the implant of the drain-drift region, the PN junctions between the drain-drift region and the epitaxial layer are self-aligned with the edges of the thick bottom oxide.

Abstract: A trench MIS device is formed in a semiconductor die that contains a P-epitaxial layer that overlies an N+ substrate and an N-epitaxial layer. In one embodiment, the device includes a drain-drift region that extends from the bottom of the trench to the N-epitaxial layer. A termination region of the die includes a half-trench at an edge of the die and an N-type region that extends from a bottom of the half-trench to the substrate. An insulating layer and an overlying metal layer extend from the surface of the epitaxial layer into the half-trench. Preferably, the elements of the termination region are formed during the same process steps that are used to form the active elements of the device.

Abstract: A trench MIS device is formed in a P-epitaxial layer that overlies an N-epitaxial layer and an N+ substrate. In one embodiment, the device includes an N-type drain-drift region that extends from the bottom of the trench to the N-epitaxial layer. Preferably, the drain-drift region is formed at least in part by fabricating spacers on the sidewalls of the trench and implanting an N-type dopant between the sidewall spacers and through the bottom of the trench. The drain-drift region can be doped more heavily than the conventional“drift region” that is formed in an N-epitaxial layer. Thus, the device has a low on-resistance. The device can be terminated by a plurality of polysilicon-filled termination trenches located near the edge of the die, with the polysilicon in each termination trench being connected to the mesa adjacent the termination trench. The polysilicon material in each termination trenches.

Abstract: A high-voltage transistor with a low specific on-state resistance and that supports high voltage in the off-state includes one or more source regions disposed adjacent to a multi-layered extended drain structure which comprises extended drift regions separated from field plate members by one or more dielectric layers. With the field plate members at the lowest circuit potential, the transistor supports high voltages applied to the drain in the off-state. The layered structure may be fabricated in a variety of orientations. A MOSFET structure may be incorporated into the device adjacent to the source region, or, alternatively, the MOSFET structure may be omitted to produce a high-voltage transistor structure having a stand-alone drift region.

Abstract: A high-voltage transistor with a low specific on-state resistance and that supports high voltage in the off-state includes one or more source regions disposed adjacent to a multi-layered extended drain structure which comprises extended drift regions separated from field plate members by one or more dielectric layers. With the field plate members at the lowest circuit potential, the transistor supports high voltages applied to the drain in the off-state. The layered structure may be fabricated in a variety of orientations. A MOSFET structure may be incorporated into the device adjacent to the source region, or, alternatively, the MOSFET structure may be omitted to produce a high-voltage transistor structure having a stand-alone drift region.

Abstract: A high-voltage transistor with a low specific on-state resistance and that supports high voltage in the off-state includes one or more source regions disposed adjacent to a multi-layered extended drain structure which comprises extended drift regions separated from field plate members by one or more dielectric layers. With the field plate members at the lowest circuit potential, the transistor supports high voltages applied to the drain in the off-state. The layered structure may be fabricated in a variety of orientations. A MOSFET structure may be incorporated into the device adjacent to the source region, or, alternatively, the MOSFET structure may be omitted to produce a high-voltage transistor structure having a stand-alone drift region.

Abstract: A high-voltage transistor with a low specific on-state resistance and that supports high voltage in the off-state includes one or more source regions disposed adjacent to a multi-layered extended drain structure which comprises extended drift regions separated from field plate members by one or more dielectric layers. With the field plate members at the lowest circuit potential, the transistor supports high voltages applied to the drain in the off-state. The layered structure may be fabricated in a variety of orientations. A MOSFET structure may be incorporated into the device adjacent to the source region, or, alternatively, the MOSFET structure may be omitted to produce a high-voltage transistor structure having a stand-alone drift region.

Abstract: A power MOSFET or other semiconductor device contains a layer of silicon combined with germanium to reduce the on-resistance of the device. The proportion of germanium in the layer is typically in the range of 1-40%. To achieve desired characteristics the concentration of germanium in the Si-Ge layer can be uniform, stepped or graded. In many embodiments it is desirable to keep the germanium below the surface of the semiconductor material to prevent germanium atoms from being incorporated into a gate oxide layer. This technique can be used in vertical DMOS and trench-gated MOSFETs, quasi-vertical MOSFETs and lateral MOSFETs, as well as insulated gate bipolar transistors, thyristors, Schottky diodes and conventional bipolar transistors.

Abstract: The gate of a MOSFET is located in a lattice of trenches which define a plurality of cells. Most of the cells contain a MOSFET, but a selected number of the cells at predetermined locations in the lattice contain either a PN diode or a Schottky diode. The PN and Schottky diodes are connected in parallel with the channels in the MOSFET cells, with their anodes tied to the anode of the parasitic diodes in the MOSFET cells and their cathodes tied to the cathode of the parasitic diodes. When the MOSFET is biased in the normal direction (with the parasitic diode reverse-biased), the PN diodes provide a predictable breakdown voltage for the device and ensure that avalanche breakdown occurs at a location away from the trench gate where the hot carriers generated by the breakdown cannot damage the oxide layer which lines the walls of the trench. When the device is biased in the opposite direction, the Schottky diodes conduct and thereby limit charge storage at the PN junctions in the diode and MOSFET cells.

Abstract: A trenched-gate power MOSFET includes a body region that is formed within a mesa between adjacent gate trenches. The doping concentration of the body region is established such that the body region does not fully deplete at normal drain voltages. The MOSFET also includes a gate which is doped with material of a conductivity type opposite to that of the body. The width of the mesa and the doping concentration of the body region and gate are established such that the body region is fully depleted by the combined effects of the source-body and drain body junctions and the gate. As a result, the conventional source-body short can be eliminated, providing a greater cell packing density and lower on-resistance while maintaining acceptable levels of leakage current when the MOSFET is in the off-state.

Abstract: The cell density of a trenched DMOS transistor is increased by overcoming the problem of lateral diffusion of deep P+body regions. This problem is solved in three versions. In a first version, the deep P+body region is formed using a high energy implant into a single epitaxial layer. In a second version, a double epitaxial layer is used with a somewhat lower but still high energy deep P+body implant. In a third version, there is no deep P+body implant but only the double epitaxial layer is used. The cell density is improved to more than 12 million cells per square inch in each of the three versions.