Abstract: Systems, methods, and apparatuses relating to instructions to multiply floating-point values of about zero are described.

Abstract: Systems, methods, and apparatuses relating to instructions to multiply values of zero are described.

Abstract: A system for autonomous and proactive power management for energy efficient execution of machine learning workloads may include an apparatus such as system-on-chip (SoC) comprising an accelerator configurable to load and execute a neural network and circuitry to receive a profile of the neural network. The profile may be received from a compiler and include information regarding a plurality of layers of the neural network. Responsive to the profile and the information regarding the plurality of layers, circuitry may adjust, using a local power management unit (PMU) included the apparatus, a power level to the accelerator while the accelerator executes the neural network. The power level adjustment may be based on whether the particular layer is a compute-intensive layer or a memory-intensive layer.

Abstract: Systems, methods, and apparatuses relating to instructions to multiply floating-point values of about one are described.

Abstract: Technology for estimating neural network (NN) power profiles includes obtaining a plurality of workloads for a compiled NN model, the plurality of workloads determined for a hardware execution device, determining a hardware efficiency factor for the compiled NN model, and generating, based on the hardware efficiency factor, a power profile for the compiled NN model on one or more of a per-layer basis or a per-workload basis. The hardware efficiency factor can be determined on based on a hardware efficiency measurement and a hardware utilization measurement, and can be determined on a per-workload basis. A configuration file can be provided for generating the power profile, and an output visualization of the power profile can be generated. Further, feedback information can be generated to perform one or more of selecting a hardware device, optimizing a breakdown of workloads, optimizing a scheduling of tasks, or confirming a hardware device design.

Abstract: Embodiments of apparatuses, methods, and systems for a generic linear unit hardware accelerator are disclosed. In an embodiment, an apparatus includes a comparator, an exponential subunit, a multiplier subunit, and an adder subunit. The apparatus is to receive an input tensor, a threshold, an exponential enable, a scaling factor, and a bias factor and is to perform a transformation function on the input tensor to generate an output tensor.

Abstract: Systems, methods, and apparatuses relating to instructions to multiply values of one are described.

Abstract: Systems, methods, and apparatuses relating to instructions to multiply floating-point values of about one are described.

Abstract: Systems, methods, and apparatuses relating to instructions to multiply floating-point values of about zero are described.

Abstract: Systems, methods, and apparatuses relating to instructions to multiply values of zero are described.

Abstract: Examples to determine a dynamic batch size of a layer are disclosed herein. An example apparatus to determine a dynamic batch size of a layer includes a layer operations controller to determine a layer ratio between a number of operations of a layer and weights of the layer, a comparator to compare the layer ratio to a number of operations per unit of memory size performed by a computation engine, and a batch size determination controller to, when the layer ratio is less than the number of operations per unit of memory size, determine the dynamic batch size of the layer.

Abstract: Methods, systems, and articles herein are directed to event-driven object segmentation to track events rather than tracking all pixel locations in an image.