Patents by Inventor Mohamed Hassan Abu-Rahma
Mohamed Hassan Abu-Rahma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9875788Abstract: A 5 Transistor Static Random Access Memory (5T SRAM) is designed for reduced cell size and immunity to process variation. The 5T SRAM includes a storage element for storing data, wherein the storage element is coupled to a first voltage and a ground voltage. The storage element can include symmetrically sized cross-coupled inverters. A single access transistor controls read and write operations on the storage element. Control logic is configured to generate a value of the first voltage a write operation that is different from the value of the first voltage for a read operation.Type: GrantFiled: March 25, 2010Date of Patent: January 23, 2018Assignee: QUALCOMM IncorporatedInventors: Seong-Ook Jung, Hyunkook Park, Seung-Chul Song, Mohamed Hassan Abu-Rahma, Lixin Ge, Zhongze Wang, Beom-Mo Han
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Patent number: 9698267Abstract: A transistor is disclosed and includes forming a gate of a transistor within a substrate having a surface and a buried oxide (BOX) layer within the substrate and adjacent to the gate at a first BOX layer face. The method also includes a raised source-drain channel (“fin”), where at least a portion of the fin extends from the surface of the substrate, and where the fin has a first fin face adjacent to a second BOX layer face of the BOX layer.Type: GrantFiled: July 1, 2014Date of Patent: July 4, 2017Assignee: QUALCOMM IncorporatedInventors: Stanley Seungchul Song, Mohamed Hassan Abu-Rahma, Beom-Mo Han
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Patent number: 9673786Abstract: A circuit including a logic gate responsive to a clock signal and to a control signal. The circuit also includes a master stage of a flip-flop. The circuit further includes a slave stage of the flip-flop responsive to the master stage. The circuit further includes an inverter responsive to the logic gate and configured to output a delayed version of the clock signal. An output of the logic gate and the delayed version of the clock signal are provided to the master stage and to the slave stage of the flip-flop. The master stage is responsive to the control signal to control the slave stage.Type: GrantFiled: April 12, 2013Date of Patent: June 6, 2017Assignee: QUALCOMM IncorporatedInventors: Seid Hadi Rasouli, Animesh Datta, Jay Madhukar Shah, Martin Saint-Laurent, Peeyush Kumar Parkar, Sachin Bapat, Ramaprasath Vilangudipitchai, Mohamed Hassan Abu-Rahma, Prayag Bhanubhai Patel
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Patent number: 9337100Abstract: An apparatus and method to fabricate an electronic device is disclosed. In a particular embodiment, an apparatus includes a template having an imprint surface. The imprint surface includes a first region having a first pattern adapted to fabricate a fin field effect transistor (FinFET) device and a second region having a second pattern adapted to fabricate a planar electronic device.Type: GrantFiled: June 3, 2009Date of Patent: May 10, 2016Assignee: QUALCOMM IncorporatedInventors: Seung-Chul Song, Beom-Mo Han, Mohamed Hassan Abu-Rahma
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Patent number: 9224453Abstract: A write-assisted memory includes a pre-charge assist circuit that assists the pre-charge of the power supply voltage on a power supply lead for an accessed memory cell in a bit-line-multiplexed group of memory cells subsequent to a write-assist period by coupling charge from the power supply leads for the remaining non-accessed memory cells in the bit-line-multiplexed group of memory cells.Type: GrantFiled: March 13, 2013Date of Patent: December 29, 2015Assignee: QUALCOMM IncorporatedInventors: Peng Jin, Mohamed Hassan Abu-Rahma, Fahad Ahmed
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Patent number: 9092013Abstract: Time-to-digital converters (TDC) with improved resistance to metastability are provided. The TDC includes a ring oscillator gated by a start signal. A stop signal triggers capturing values of phase signals from the ring oscillator using master-slave flip-flops. Signals from two of the master stages of the flip-flops are logically combined to produce a counter clock signal that causes a counter to count. The outputs of the flip-flops and of the counter are encoded to produce a digital representation of the time between transitions of the start signal and the stop signal. Since the signals from the master stages of flip-flops are captured (and stop toggling) by the stop signal, the counter clock signal stops toggling, and the counter stops counting. This assures that the values of the captured phase signals and the counter are consistent and avoids metastability errors that could otherwise occur.Type: GrantFiled: September 17, 2013Date of Patent: July 28, 2015Assignee: QUALCOMM IncorporatedInventors: Hui William Song, Mohamed Hassan Abu-Rahma
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Patent number: 9052725Abstract: An apparatus and method for controlling power supplied to data generating circuits based on performance, such as time delay associated with generating data. The apparatus includes a plurality of data generating circuits configured to generate data at respective outputs in response to a first signal; a plurality of timing circuits configured to generate a plurality of second signals related to time delays between the first signal initiating the generation of the data and an appearance of the data at the respective outputs of the data generating circuits; a power supply circuit configured to generate a voltage for supplying power to the data generating circuits; a power controller configured to control the voltage generated by the power supply circuit based on the plurality of second signals; and a serial data transfer circuit configured to serial transfer the plurality of second signals from the respective timing circuits to the power controller.Type: GrantFiled: November 15, 2013Date of Patent: June 9, 2015Assignee: QUALCOMM IncorporatedInventors: Hui William Song, Mohamed Hassan Abu-Rahma, Esin Terizioglu
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Publication number: 20150137879Abstract: An apparatus and method for controlling power supplied to data generating circuits based on performance, such as time delay associated with generating data. The apparatus includes a plurality of data generating circuits configured to generate data at respective outputs in response to a first signal; a plurality of timing circuits configured to generate a plurality of second signals related to time delays between the first signal initiating the generation of the data and an appearance of the data at the respective outputs of the data generating circuits; a power supply circuit configured to generate a voltage for supplying power to the data generating circuits; a power controller configured to control the voltage generated by the power supply circuit based on the plurality of second signals; and a serial data transfer circuit configured to serial transfer the plurality of second signals from the respective timing circuits to the power controller.Type: ApplicationFiled: November 15, 2013Publication date: May 21, 2015Applicant: QUALCOMM IncorporatedInventors: Hui William Song, Mohamed Hassan Abu-Rahma, Esin Terizioglu
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Patent number: 9019751Abstract: Various integrated circuits and methods of operating the integrated circuits are disclosed. The integrated circuit may include a circuit having one or more electrical parameters resulting from process variations during the manufacture of the integrated circuit, and a voltage source configured to supply a voltage to the circuit to power the circuit, wherein the voltage source is further configured to adjust the voltage as a function of the one or more electrical parameters.Type: GrantFiled: March 1, 2013Date of Patent: April 28, 2015Assignee: QUALCOMM IncorporatedInventors: Peng Jin, Mohamed Hassan Abu-Rahma, Fahad Ahmed, Jaeyoon Kim
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Publication number: 20150077279Abstract: Time-to-digital converters (TDC) with improved resistance to metastability are provided. The TDC includes a ring oscillator gated by a start signal. A stop signal triggers capturing values of phase signals from the ring oscillator using master-slave flip-flops. Signals from two of the master stages of the flip-flops are logically combined to produce a counter clock signal that causes a counter to count. The outputs of the flip-flops and of the counter are encoded to produce a digital representation of the time between transitions of the start signal and the stop signal. Since the signals from the master stages of flip-flops are captured (and stop toggling) by the stop signal, the counter clock signal stops toggling, and the counter stops counting. This assures that the values of the captured phase signals and the counter are consistent and avoids metastability errors that could otherwise occur.Type: ApplicationFiled: September 17, 2013Publication date: March 19, 2015Applicant: QUALCOMM IncorporatedInventors: Hui William Song, Mohamed Hassan Abu-Rahma
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Patent number: 8976574Abstract: An integrated circuit is disclosed. The integrated circuit includes a plurality of bit-cells arranged to store data. The integrated circuit also includes a sensor configured to generate an output for determining whether the bit-cells are operating at a process corner. The sensor comprises the same circuitry as the bit-cells.Type: GrantFiled: March 13, 2013Date of Patent: March 10, 2015Assignee: QUALCOMM IncorporatedInventors: Fahad Ahmed, Mohamed Hassan Abu-Rahma, Peng Jin
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Publication number: 20140313821Abstract: A fin-type device system and method is disclosed. In a particular embodiment, a transistor is disclosed and includes forming a gate of a transistor within a substrate having a surface and a buried oxide (BOX) layer within the substrate and adjacent to the gate at a first BOX layer face. The method also includes a raised source-drain channel (“fin”), where at least a portion of the fin extends from the surface of the substrate, and where the fin has a first fin face adjacent to a second BOX layer face of the BOX layer.Type: ApplicationFiled: July 1, 2014Publication date: October 23, 2014Inventors: Stanley Seungchul SONG, Mohamed Hassan ABU-RAHMA, Beom-Mo HAN
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Publication number: 20140306735Abstract: A circuit including a logic gate responsive to a clock signal and to a control signal. The circuit also includes a master stage of a flip-flop. The circuit further includes a slave stage of the flip-flop responsive to the master stage. The circuit further includes an inverter responsive to the logic gate and configured to output a delayed version of the clock signal. An output of the logic gate and the delayed version of the clock signal are provided to the master stage and to the slave stage of the flip-flop. The master stage is responsive to the control signal to control the slave stage.Type: ApplicationFiled: April 12, 2013Publication date: October 16, 2014Applicant: QUALCOMM IncorporatedInventors: Seid Hadi Rasouli, Animesh Datta, Jay Madhukar Shah, Martin Saint-Laurent, Peeyush Kumar Parkar, Sachin Bapat, Ramaprasath Vilangudipitchai, Mohamed Hassan Abu-Rahma, Prayag Bhanubhai Patel
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Publication number: 20140269017Abstract: An integrated circuit is disclosed. The integrated circuit includes a plurality of bit-cells arranged to store data. The integrated circuit also includes a sensor configured to generate an output for determining whether the bit-cells are operating at a process corner. The sensor comprises the same circuitry as the bit-cells.Type: ApplicationFiled: March 13, 2013Publication date: September 18, 2014Applicant: QUALCOMM IncorporatedInventors: Fahad Ahmed, Mohamed Hassan Abu-Rahma, Peng Jin
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Publication number: 20140269018Abstract: A write-assisted memory includes a pre-charge assist circuit that assists the pre-charge of the power supply voltage on a power supply lead for an accessed memory cell in a bit-line-multiplexed group of memory cells subsequent to a write-assist period by coupling charge from the power supply leads for the remaining non-accessed memory cells in the bit-line-multiplexed group of memory cells.Type: ApplicationFiled: March 13, 2013Publication date: September 18, 2014Applicant: QUALCOMM IncorporatedInventors: Peng Jin, Mohamed Hassan Abu-Rahma, Fahad Ahmed
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Publication number: 20140247652Abstract: Various integrated circuits and methods of operating the integrated circuits are disclosed. The integrated circuit may include a circuit having one or more electrical parameters resulting from process variations during the manufacture of the integrated circuit, and a voltage source configured to supply a voltage to the circuit to power the circuit, wherein the voltage source is further configured to adjust the voltage as a function of the one or more electrical parameters.Type: ApplicationFiled: March 1, 2013Publication date: September 4, 2014Applicant: QUALCOMM IncorporatedInventors: Peng Jin, Mohamed Hassan Abu-Rahma, Fahad Ahmed, Jaeyoon Kim
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Patent number: 8228714Abstract: In a particular embodiment, a memory device is disclosed that includes a memory cell including a resistance-based memory element coupled to an access transistor. The access transistor has a first oxide thickness to enable operation of the memory cell at an operating voltage. The memory device also includes a first amplifier configured to couple the memory cell to a supply voltage that is greater than a voltage limit to generate a data signal based on a current through the memory cell. The first amplifier includes a clamp transistor that has a second oxide thickness that is greater than the first oxide thickness. The clamp transistor is configured to prevent the operating voltage at the memory cell from exceeding the voltage limit.Type: GrantFiled: September 9, 2008Date of Patent: July 24, 2012Assignee: QUALCOMM IncorporatedInventors: Anosh B. Davierwalla, Cheng Zhong, Dongkyu Park, Mohamed Hassan Abu-Rahma, Mehdi Hamidi Sani, Sei Seung Yoon
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Patent number: 8199602Abstract: Reduction of line delay is accomplished in an electronic memory by segmenting portions of the memory and only enabling certain memory portions depending upon where the memory is to be accessed. In one embodiment, the bit lines are segmented using latch repeaters to control the bit line length for address selection. The latch repeaters are, in one embodiment, allowed to remain in their operated/non-operated state at the completion of a memory read/write cycle. This then avoids successive enabling pulses when the same segment is accessed on successive cycles.Type: GrantFiled: July 30, 2010Date of Patent: June 12, 2012Assignee: QUALCOMM IncorporatedInventors: Hari Rao, Dongkyu Park, Mohamed Hassan Abu-Rahma
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Patent number: 8130534Abstract: A system and method to read and write data in magnetic random access memories are disclosed. In a particular embodiment, a device includes a spin transfer torque magnetic tunnel junction (STT-MTJ) element and a transistor with a first gate and a second gate coupled to the STT-MTJ element.Type: GrantFiled: January 8, 2009Date of Patent: March 6, 2012Assignee: QUALCOMM IncorporatedInventors: Mohamed Hassan Abu-Rahma, Seung-Chul Song, Sei Seung Yoon, Dongkyu Park, Cheng Zhong, Anosh B. Davierwalla
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Publication number: 20110235406Abstract: A 5 Transistor Static Random Access Memory (5T SRAM) is designed for reduced cell size and immunity to process variation. The 5T SRAM includes a storage element for storing data, wherein the storage element is coupled to a first voltage and a ground voltage. The storage element can include symmetrically sized cross-coupled inverters. A single access transistor controls read and write operations on the storage element. Control logic is configured to generate a value of the first voltage a write operation that is different from the value of the first voltage for a read operation.Type: ApplicationFiled: March 25, 2010Publication date: September 29, 2011Applicants: QUALCOMM INCORPORATED, Industry-Academic Cooperation Foundation, Yonsei UniversityInventors: Seong-Ook Jung, Hyunkook Park, Seung-Chul Song, Mohamed Hassan Abu-Rahma, Lixin Ge, Zhongze Wang, Beom-Mo Han