Patents by Inventor Mohamed Lachab

Mohamed Lachab has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor heterostructure with p-type superlattice
    Patent number: 11984529
    Abstract: A heterostructure for an optoelectronic device is disclosed. The heterostructure includes an active region including at least one quantum well and at least one barrier and an electron blocking layer located adjacent to the active region, wherein the electron blocking layer includes a region of graded composition. An asymmetric p-type superlattice layer is located adjacent to the electron blocking layer, wherein the p-type superlattice includes at least one superlattice period comprising a set of wells and a set of barriers. A thickness of at least one of: each well in the set of wells or each barrier in the set of barriers varies along a length of the p-type superlattice.
    Type: Grant
    Filed: July 16, 2020
    Date of Patent: May 14, 2024
    Assignee: Sensor Electronic Technology, Inc.
    Inventor: Mohamed Lachab
  • Dislocation Reduction in Semiconductor Compounds
    Publication number: 20230299238
    Abstract: A solution for fabricating a semiconductor structure and the corresponding semiconductor structure are provided. The semiconductor structure includes a plurality of semiconductor layers grown over a substrate using a set of epitaxial growth periods. During each epitaxial growth period, a first semiconductor layer having one of: a tensile stress or a compressive stress is grown followed by growth of a second semiconductor layer having the other of: the tensile stress or the compressive stress directly on the first semiconductor layer.
    Type: Application
    Filed: March 16, 2023
    Publication date: September 21, 2023
    Inventors: Rakesh B. Jain, Mohamed Lachab, Joseph Dion, Brandon Alexander Robinson, Devendra Diwan, Mark Geppert
  • Semiconductor Heterostructure with P-type Superlattice
    Publication number: 20200350465
    Abstract: A heterostructure for an optoelectronic device is disclosed. The heterostructure includes an active region including at least one quantum well and at least one barrier and an electron blocking layer located adjacent to the active region, wherein the electron blocking layer includes a region of graded composition. An asymmetric p-type superlattice layer is located adjacent to the electron blocking layer, wherein the p-type superlattice includes at least one superlattice period comprising a set of wells and a set of barriers. A thickness of at least one of: each well in the set of wells or each barrier in the set of barriers varies along a length of the p-type superlattice.
    Type: Application
    Filed: July 16, 2020
    Publication date: November 5, 2020
    Applicant: Sensor Electronic Technology, Inc.
    Inventor: Mohamed Lachab
  • Semiconductor Heterostructure with P-type Superlattice
    Publication number: 20190103509
    Abstract: A heterostructure for an optoelectronic device is disclosed. The heterostructure includes an active region including at least one quantum well and at least one barrier and an electron blocking layer located adjacent to the active region, wherein the electron blocking layer includes a region of graded composition. An asymmetric p-type superlattice layer is located adjacent to the electron blocking layer, wherein the p-type superlattice includes at least one superlattice period comprising a set of wells and a set of barriers. A thickness of at least one of: each well in the set of wells or each barrier in the set of barriers varies along a length of the p-type superlattice.
    Type: Application
    Filed: October 1, 2018
    Publication date: April 4, 2019
    Applicant: Sensor Electronic Technology, Inc.
    Inventor: Mohamed Lachab