Abstract: An apparatus includes a sample-and-hold (S/H) circuit. The S/H circuit includes a first switch coupled to provide an input signal to be sampled, and a second switch coupled to the first switch and to a first capacitor. The S/H circuit further includes a third switch coupled to the second switch and to a second capacitor, and a fourth switch to selectively couple to ground a node between the first and second switches.

Abstract: An apparatus includes an integrated circuit (IC), which includes complementary metal oxide semiconductor (CMOS) circuitry. The CMOS circuitry includes a p-channel transistor network that includes at least one p-channel transistor having a gate-induced drain leakage (GIDL) current. The IC further includes a native metal oxide semiconductor (MOS) transistor coupled to supply a bias voltage to the at least one p-channel transistor to reduce the GIDL current of the at least one p-channel transistor.

Abstract: An apparatus includes a sample-and-hold (S/H) circuit. The S/H circuit includes a first switch coupled to provide an input signal to be sampled, and a second switch coupled to the first switch and to a first capacitor. The S/H circuit further includes a third switch coupled to the second switch and to a second capacitor, and a fourth switch to selectively couple to ground a node between the first and second switches.

Abstract: An apparatus includes a sample-and-hold (S/H) circuit. The S/H circuit includes a first switch coupled to provide an input signal to be sampled, and a second switch coupled to the first switch and to a first capacitor. The S/H circuit further includes a third switch coupled to the second switch and to a second capacitor, and a fourth switch to selectively couple to ground a node between the first and second switches.

Abstract: Embodiments of improved CMOS input stage circuits and related methods are provided herein to maintain a near constant transconductance across an entire common-mode input voltage range of the input stage. One embodiment includes a pair of NMOS input transistors and a pair of PMOS input transistors, each coupled to receive a differential input voltages at their gate terminals; a current source coupled to source terminals of the pair of PMOS input transistors and configured to generate a current; a current steering circuit configured to steer the current to the pair of NMOS input transistors and/or to the pair of PMOS input transistors, depending on whether a common mode input voltage (CMV) is greater than, less than, or substantially equal to a cross-over voltage; and a current stealing circuit configured to reduce the current when the CMV is substantially equal to the cross-over voltage.

Abstract: Embodiments of improved CMOS input stage circuits and related methods are provided herein to maintain a near constant transconductance across an entire common-mode input voltage range of the input stage. One embodiment includes a pair of NMOS input transistors and a pair of PMOS input transistors, each coupled to receive a differential input voltages at their gate terminals; a current source coupled to source terminals of the pair of PMOS input transistors and configured to generate a current; a current steering circuit configured to steer the current to the pair of NMOS input transistors and/or to the pair of PMOS input transistors, depending on whether a common mode input voltage (CMV) is greater than, less than, or substantially equal to a cross-over voltage; and a current stealing circuit configured to reduce the current when the CMV is substantially equal to the cross-over voltage.

Abstract: An apparatus includes a temperature measurement circuit. The temperature measurement circuit includes a bandgap circuit including an amplifier having an offset voltage that is compensated by using a set of trimming bits. The bandgap circuit provides first and second voltages related to a temperature to be measured. The temperature measurement circuit further includes a measuring circuit coupled to receive the first and second voltages. The measuring circuit further includes a comparator coupled to receive the first and second voltages, wherein the measuring circuit derives a temperature measurement from the first and second voltages.

Abstract: An apparatus includes an integrated circuit (IC), which includes complementary metal oxide semiconductor (CMOS) circuitry. The CMOS circuitry includes a p-channel transistor network that includes at least one p-channel transistor having a gate-induced drain leakage (GIDL) current. The IC further includes a native metal oxide semiconductor (MOS) transistor coupled to supply a bias voltage to the at least one p-channel transistor to reduce the GIDL current of the at least one p-channel transistor.

Abstract: An apparatus includes an integrated circuit (IC), which includes complementary metal oxide semiconductor (CMOS) circuitry. The CMOS circuitry includes a p-channel transistor network that includes at least one p-channel transistor having a gate-induced drain leakage (GIDL) current. The IC further includes a native metal oxide semiconductor (MOS) transistor coupled to supply a bias voltage to the at least one p-channel transistor to reduce the GIDL current of the at least one p-channel transistor.

Abstract: A method for bidirectional hyperlink management of a hypertext associated with an on-line media is provided. The method may include searching the on-line media for at least one keyword associated with the hypertext. The method may also include scanning a website associated with the hypertext based on the search of the at least one keyword. The method may further include locating at least one dead-link uniform resource locator (URL) associated with the scanned website. Additionally, the method may include managing the at least one located dead-link based on a set of pre-defined rules associated with the on-line media.

Abstract: An apparatus includes a sample-and-hold (S/H) circuit. The S/H circuit includes a first switch to provide an input signal that is to be sampled, and a second switch coupled to receive the sampled signal. The second switch is further coupled to a capacitor. The S/H circuit further includes at least one native transistor coupled to the second switch and to the capacitor.

Abstract: An apparatus includes a sample-and-hold (S/H) circuit. The S/H circuit includes a first switch coupled to receive an input signal. The first switch is further coupled to a first capacitor. The S/H circuit further includes a buffer coupled to the first switch. In addition, the S/H circuit includes a voltage source coupled to an input of the buffer to apply an offset voltage to the input of the buffer.

Abstract: An apparatus includes a temperature measurement circuit. The temperature measurement circuit includes a bandgap circuit including an amplifier having an offset voltage that is compensated by using a set of trimming bits. The bandgap circuit provides first and second voltages related to a temperature to be measured. The temperature measurement circuit further includes a measuring circuit coupled to receive the first and second voltages. The measuring circuit further includes a comparator coupled to receive the first and second voltages, wherein the measuring circuit derives a temperature measurement from the first and second voltages.

Abstract: An apparatus includes a sample-and-hold (S/H) circuit. The S/H circuit includes a first switch coupled to receive an input signal. The first switch is further coupled to a first capacitor. The S/H circuit further includes a buffer coupled to the first switch. In addition, the S/H circuit includes a voltage source coupled to an input of the buffer to apply an offset voltage to the input of the buffer.

Abstract: An apparatus includes a sample-and-hold (S/H) circuit. The S/H circuit includes a first switch to provide an input signal that is to be sampled, and a second switch coupled to receive the sampled signal. The second switch is further coupled to a capacitor. The S/H circuit further includes at least one native transistor coupled to the second switch and to the capacitor.

Abstract: An apparatus includes a sample-and-hold (S/H) circuit. The S/H circuit includes a first switch coupled to provide an input signal to be sampled, and a second switch coupled to the first switch and to a first capacitor. The S/H circuit further includes a third switch coupled to the second switch and to a second capacitor, and a fourth switch to selectively couple to ground a node between the first and second switches.

Abstract: An apparatus includes an integrated circuit (IC), which includes complementary metal oxide semiconductor (CMOS) circuitry. The CMOS circuitry includes a p-channel transistor network that includes at least one p-channel transistor having a gate-induced drain leakage (GIDL) current. The IC further includes a native metal oxide semiconductor (MOS) transistor coupled to supply a bias voltage to the at least one p-channel transistor to reduce the GIDL current of the at least one p-channel transistor.

Abstract: Embodiments of bias current generator circuits are provided herein for generating stable bias currents. In one embodiment, a bias current generator circuit may include a voltage-to-current generating circuit, an integrate and hold circuit, an amplifier circuit and a plurality of output branches. The voltage-to-current generating circuit may supply a first current to a first node of the bias current generator circuit. The integrate and hold circuit may receive a second current, which is equal to a difference between the first current and a reference current, from the first node and may generate a first voltage in response thereto. The amplifier circuit may receive the first voltage generated by the integrate and hold circuit, and may generate a second voltage in response to the first voltage. The plurality of output branches may receive the second voltage, and may generate a plurality of bias currents in response thereto.

Abstract: A method for bidirectional hyperlink management of a hypertext associated with an on-line media is provided. The method may include searching the on-line media for at least one keyword associated with the hypertext. The method may also include scanning a website associated with the hypertext based on the search of the at least one keyword. The method may further include locating at least one dead-link uniform resource locator (URL) associated with the scanned website. Additionally, the method may include managing the at least one located dead-link based on a set of pre-defined rules associated with the on-line media.

Abstract: A method for bidirectional hyperlink management of a hypertext associated with an on-line media is provided. The method may include searching the on-line media for at least one keyword associated with the hypertext. The method may also include scanning a website associated with the hypertext based on the search of the at least one keyword. The method may further include locating at least one dead-link uniform resource locator (URL) associated with the scanned website. Additionally, the method may include managing the at least one located dead-link based on a set of pre-defined rules associated with the on-line media.