Patents by Inventor Mohamed Mobarak

Mohamed Mobarak has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11404779
    Abstract: Aspects of this disclosure relate to systems and methods for calibration of antenna arrays. The calibration may be based on determining a reference value for the beamformer derived from measurements of phase and/or amplitude for each channel within the beamformer. The measurements of phase and/or amplitude can be stored in non-volatile memory. Using a difference between the reference value and the measured values for each channel, a portion of a global configuration table may be copied to each channel's memory. Each channel can be separately calibrated based on the portion of the global configuration table copied to the local memory of each channel.
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: August 2, 2022
    Assignee: Analog Devices International Unlimited Company
    Inventors: Mohamed Mobarak, Ahmed Khalil
  • Patent number: 11303309
    Abstract: Bias arrangements for amplifiers are disclosed. An example arrangement includes a bias circuit, configured to produce a bias signal for the amplifier, and a linearization circuit, configured to improve linearity of the amplifier by modifying the bias signal based on an RF signal indicative of an RF input signal to be amplified by the amplifier. The linearization circuit includes a bias signal input for receiving the bias signal, an RF signal input for receiving the RF signal, and an output for providing a modified bias signal. The linearization circuit further includes at least a first linearization transistor, having a first terminal, a second terminal, and a third terminal, where each of the bias signal input and the RF signal input of the linearization circuit is coupled to the first terminal of the first linearization transistor, and the output of the linearization circuit is coupled to the third terminal of the first linearization transistor.
    Type: Grant
    Filed: October 7, 2020
    Date of Patent: April 12, 2022
    Assignee: Analog Devices International Unlimited Company
    Inventors: Mohamed Mobarak, Mohamed Moussa Ramadan Esmael, Mohamed Weheiba
  • Patent number: 11265027
    Abstract: Bias arrangements for amplifiers are disclosed. An example arrangement includes a bias circuit, configured to produce a bias signal for the amplifier, and a linearization circuit, configured to improve linearity of the amplifier by modifying the bias signal based on an RF signal indicative of an RF input signal to be amplified by the amplifier. The linearization circuit includes a bias signal input for receiving the bias signal, an RF signal input for receiving the RF signal, and an output for providing a modified bias signal. The linearization circuit further includes at least a first linearization transistor, having a first terminal, a second terminal, and a third terminal, where each of the bias signal input and the RF signal input of the linearization circuit is coupled to the first terminal of the first linearization transistor, and the output of the linearization circuit is coupled to the third terminal of the first linearization transistor.
    Type: Grant
    Filed: October 7, 2020
    Date of Patent: March 1, 2022
    Assignee: Analog Devices International Unlimited Company
    Inventors: Mohamed Mobarak, Mohamed Moussa Ramadan Esmael, Mohamed Weheiba
  • Patent number: 11264953
    Abstract: Bias arrangements for amplifiers are disclosed. An example bias arrangement for an amplifier includes a bias circuit, configured to produce a bias signal for the amplifier; a linearization circuit, configured to improve linearity of the amplifier by modifying the bias signal produced by the bias circuit to produce a modified bias signal to be provided to the amplifier; and a coupling circuit, configured to couple the bias circuit and the linearization circuit. Providing separate bias and linearization circuits coupled to one another by a coupling circuit allows separating a linearization operation from a biasing loop to overcome some drawbacks of prior art bias arrangements that utilize a single biasing loop.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: March 1, 2022
    Assignee: ANALOG DEVICES INTERNATIONAL UNLIMITED COMPANY
    Inventors: Mohamed Mobarak, Mohamed Weheiba, Mohamed Moussa Ramadan Esmael
  • Patent number: 11177567
    Abstract: Aspects of this disclosure relate to an antenna array system and method of calibration using one or more probes disposed equidistant between antenna elements. In certain embodiments, calibration is performed between a probe and antenna elements, between a plurality of antenna elements, and/or between antenna elements on different antenna arrays.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: November 16, 2021
    Assignee: Analog Devices Global Unlimited Company
    Inventors: Ahmed I. Khalil, Mohamed Ahmed Youssef Abdalla, Islam A. Eshrah, Mohamed Mobarak
  • Publication number: 20210242835
    Abstract: Bias arrangements for amplifiers are disclosed. An example bias arrangement for an amplifier includes a bias circuit, configured to produce a bias signal for the amplifier; a linearization circuit, configured to improve linearity of the amplifier by modifying the bias signal produced by the bias circuit to produce a modified bias signal to be provided to the amplifier; and a coupling circuit, configured to couple the bias circuit and the linearization circuit. Providing separate bias and linearization circuits coupled to one another by a coupling circuit allows separating a linearization operation from a biasing loop to overcome some drawbacks of prior art bias arrangements that utilize a single biasing loop.
    Type: Application
    Filed: January 31, 2020
    Publication date: August 5, 2021
    Applicant: Analog Devices International Unlimited Company
    Inventors: Mohamed MOBARAK, Mohamed WEHEIBA, Mohamed Moussa Ramadan ESMAEL
  • Publication number: 20200295456
    Abstract: Aspects of this disclosure relate to systems and methods for calibration of antenna arrays. The calibration may be based on determining a reference value for the beamformer derived from measurements of phase and/or amplitude for each channel within the beamformer. The measurements of phase and/or amplitude can be stored in non-volatile memory. Using a difference between the reference value and the measured values for each channel, a portion of a global configuration table may be copied to each channel's memory. Each channel can be separately calibrated based on the portion of the global configuration table copied to the local memory of each channel.
    Type: Application
    Filed: January 21, 2020
    Publication date: September 17, 2020
    Inventors: Mohamed Mobarak, Ahmed Khalil
  • Publication number: 20190267707
    Abstract: Aspects of this disclosure relate to an antenna array system and method of calibration using one or more probes disposed equidistant between antenna elements. In certain embodiments, calibration is performed between a probe and antenna elements, between a plurality of antenna elements, and/or between antenna elements on different antenna arrays.
    Type: Application
    Filed: February 23, 2018
    Publication date: August 29, 2019
    Inventors: Ahmed I. Khalil, Mohamed Ahmed Youssef Abdalla, Islam A. Eshrah, Mohamed Mobarak
  • Patent number: 10200009
    Abstract: A transformer-based balun circuit is disclosed herein. The balun can be implemented using a spiral transformer, where primary and secondary transformer windings can be inductively coupled and can be implemented on the same metal layer (or different metal layers, e.g. vertically adjacent metal layers). The balun can further include a compensation capacitor and a digital frequency tuning circuit. The compensation capacitor can be introduced at one of the differential terminals to reduce or suppress the amplitude and phase imbalance. The digital frequency tuning circuit can be a switchable bank of capacitors, which allows for tuning the frequency of operation of the transformer-based balun.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: February 5, 2019
    Assignee: Analog Devices Global
    Inventors: Mohamed A. Abdalla, Mohamed Mobarak, Ahmed Ibrahim Khalil
  • Publication number: 20180062607
    Abstract: A transformer-based balun circuit s disclosed herein. The balun can be implemented using a spiral transformer, where primary and secondary transformer windings can be inductively coupled and can be implemented on the same metal layer (or different metal layers, e.g. vertically adjacent metal layers). The balun can further include a compensation capacitor and a digital frequency tuning circuit. The compensation capacitor can be introduced at one of the differential terminals to reduce or suppress the amplitude and phase imbalance. The digital frequency tuning circuit can be a switchable bank of capacitors, which allows for tuning the frequency of operation of the transformer-based balun.
    Type: Application
    Filed: August 31, 2016
    Publication date: March 1, 2018
    Inventors: Mohamed A. Abdalla, Mohamed Mobarak, Ahmed Ibrahim Khalil
  • Publication number: 20170302226
    Abstract: Mixers with improved linearity are disclosed. A diode or FET ring mixer is implemented with at least one parallel shunt element coupled with the ring mixer, the shunt element providing shunt to a diode or FET, for example, to reduce the effect of nonlinear or off resistance and/or capacitance. Linearity, isolation, symmetry, even order harmonics of the ring mixer, or any combination thereof can be improved as a result. The linearity of the ring mixer with parallel shunt resistors can be further improved by adding series resistors in the ring according to certain embodiments.
    Type: Application
    Filed: April 13, 2016
    Publication date: October 19, 2017
    Inventors: Mohamed Moussa Ramadan Esmael, Mohamed Mobarak
  • Patent number: 9793856
    Abstract: Mixers with improved linearity are disclosed. A diode or FET ring mixer is implemented with at least one parallel shunt element coupled with the ring mixer, the shunt element providing shunt to a diode or FET, for example, to reduce the effect of nonlinear or off resistance and/or capacitance. Linearity, isolation, symmetry, even order harmonics of the ring mixer, or any combination thereof can be improved as a result. The linearity of the ring mixer with parallel shunt resistors can be further improved by adding series resistors in the ring according to certain embodiments.
    Type: Grant
    Filed: April 13, 2016
    Date of Patent: October 17, 2017
    Assignee: Analog Devices Global
    Inventors: Mohamed Moussa Ramadan Esmael, Mohamed Mobarak