Patents by Inventor Mohamed RABIE
Mohamed RABIE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11957807Abstract: A cleaning robot may determine a three-dimensional model of a physical environment based on data collected from one or more sensors. The cleaning robot may then identify a surface within the physical environment to clean. Having identified that surface, the robot may autonomously navigate to a location proximate to the surface, position an ultraviolet light source in proximity to the surface, and activate the ultraviolet light source for a period of time.Type: GrantFiled: March 22, 2021Date of Patent: April 16, 2024Assignee: Robust AI, Inc.Inventors: Rodney Allen Brooks, Dylan Bourgeois, Crystal Chao, Alexander Jay Bruen Trevor, Mohamed Rabie Amer, Anthony Sean Jules, Gary Fred Marcus
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Patent number: 11804452Abstract: A photonic integrated circuit (PIC) structure includes an active region in at least an active layer over a substrate, the active region including a plurality of transistors therein. A plurality of dielectric interconnect layers are over the active region, and an opening is defined through the plurality of dielectric interconnect layers. The opening extends to at least the active layer. A barrier is within the plurality of dielectric interconnect layers and surrounding the opening. An optical element is positioned in the opening. The barrier prevents stress damage, such as cracks and/or delaminations, from propagating from or to the opening, and maintains the hermetic seal of the PIC structure.Type: GrantFiled: July 30, 2021Date of Patent: October 31, 2023Assignee: GLOBALFOUNDRIES U.S. Inc.Inventors: Nicholas A Polomoff, Jae Kyu Cho, Mohamed Rabie, Yunyao Jiang, Koushik Ramachandran, Pallabi Das
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Publication number: 20230030723Abstract: A photonic integrated circuit (PIC) structure includes an active region in at least an active layer over a substrate, the active region including a plurality of transistors therein. A plurality of dielectric interconnect layers are over the active region, and an opening is defined through the plurality of dielectric interconnect layers. The opening extends to at least the active layer. A barrier is within the plurality of dielectric interconnect layers and surrounding the opening. An optical element is positioned in the opening. The barrier prevents stress damage, such as cracks and/or delaminations, from propagating from or to the opening, and maintains the hermetic seal of the PIC structure.Type: ApplicationFiled: July 30, 2021Publication date: February 2, 2023Inventors: Nicholas A. Polomoff, Jae Kyu Cho, Mohamed Rabie, Yunyao Jiang, Koushik Ramachandran, Pallabi Das
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Patent number: 11569180Abstract: Structures for an optical fiber groove and methods of forming a structure for an optical fiber groove. A photonics chip includes a substrate and an interconnect structure over the substrate. The photonics chip has a first exterior corner, a second exterior corner, and a side edge extending from the first exterior corner to the second exterior corner. The substrate includes a groove positioned along the side edge between the first exterior corner and the second exterior corner. The groove is arranged to intersect the side edge at a groove corner, and the interconnect structure includes metal structures adjacent to the first groove corner. The metal structures extend diagonally in the interconnect structure relative to the side edge of the photonics chip.Type: GrantFiled: August 12, 2021Date of Patent: January 31, 2023Assignee: GlobalFoundries U.S. Inc.Inventors: Nicholas A. Polomoff, Jae Kyu Cho, Mohamed A. Rabie, Andreas D. Stricker
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Patent number: 11276651Abstract: An illustrative device disclosed herein includes a semiconductor substrate and a FinFET transistor device positioned above the semiconductor substrate, wherein the FinFET transistor device has a single active fin structure. The device also includes an electrically inactive dummy fin structure positioned adjacent the single active fin structure, wherein the electrically inactive dummy fin structure is electrically inactive with respect to electrical operation of the FinFET transistor having the single active fin.Type: GrantFiled: May 18, 2020Date of Patent: March 15, 2022Assignee: GlobalFoundries U.S. Inc.Inventors: Anton Tokranov, Kai Sun, Elizabeth Strehlow, James Mazza, David Pritchard, Heng Yang, Mohamed Rabie
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Publication number: 20210375788Abstract: Structures for an optical fiber groove and methods of forming a structure for an optical fiber groove. A photonics chip includes a substrate and an interconnect structure over the substrate. The photonics chip has a first exterior corner, a second exterior corner, and a side edge extending from the first exterior corner to the second exterior corner. The substrate includes a groove positioned along the side edge between the first exterior corner and the second exterior corner. The groove is arranged to intersect the side edge at a groove corner, and the interconnect structure includes metal structures adjacent to the first groove corner. The metal structures extend diagonally in the interconnect structure relative to the side edge of the photonics chip.Type: ApplicationFiled: August 12, 2021Publication date: December 2, 2021Inventors: Nicholas A. Polomoff, Jae Kyu Cho, Mohamed A. Rabie, Andreas D. Stricker
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Publication number: 20210358865Abstract: An illustrative device disclosed herein includes a semiconductor substrate and a FinFET transistor device positioned above the semiconductor substrate, wherein the FinFET transistor device has a single active fin structure. The device also includes an electrically inactive dummy fin structure positioned adjacent the single active fin structure, wherein the electrically inactive dummy fin structure is electrically inactive with respect to electrical operation of the FinFET transistor having the single active fin.Type: ApplicationFiled: May 18, 2020Publication date: November 18, 2021Inventors: Anton Tokranov, Kai Sun, Elizabeth Strehlow, James Mazza, David Pritchard, Heng Yang, Mohamed Rabie
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Publication number: 20210346557Abstract: A robot may identify a human located proximate to the robot in a physical environment based on sensor data captured from one or more sensors on the robot. A trajectory of the human through space may be predicted. When the predicted trajectory of the human intersects with a current path of the robot, an updated path to a destination location in the environment may be determined so as to avoid a collision between the robot and the human along the predicted trajectory. The robot may then move along the determined path.Type: ApplicationFiled: March 19, 2021Publication date: November 11, 2021Applicant: Robust AI, Inc.Inventors: Rodney Allen Brooks, Dylan Bourgeois, Crystal Chao, Alexander Jay Bruen Trevor, Mohamed Rabie Amer, Anthony Sean Jules, Gary Fred Marcus, Michelle Ho
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Publication number: 20210346543Abstract: A cleaning robot may determine a three-dimensional model of a physical environment based on data collected from one or more sensors. The cleaning robot may then identify a surface within the physical environment to clean. Having identified that surface, the robot may autonomously navigate to a location proximate to the surface, position an ultraviolet light source in proximity to the surface, and activate the ultraviolet light source for a period of time.Type: ApplicationFiled: March 22, 2021Publication date: November 11, 2021Applicant: Robust AI, Inc.Inventors: Rodney Allen Brooks, Dylan Bourgeois, Crystal Chao, Alexander Jay Bruen Trevor, Mohamed Rabie Amer, Anthony Sean Jules, Gary Fred Marcus
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Patent number: 11145606Abstract: Structures for an optical fiber groove and methods of forming a structure for an optical fiber groove. A photonics chip includes a substrate and an interconnect structure over the substrate. The photonics chip has a first exterior corner, a second exterior corner, and a side edge extending from the first exterior corner to the second exterior corner. The substrate includes a groove positioned along the side edge between the first exterior corner and the second exterior corner. The groove is arranged to intersect the side edge at a groove corner, and the interconnect structure includes metal structures adjacent to the first groove corner. The metal structures extend diagonally in the interconnect structure relative to the side edge of the photonics chip.Type: GrantFiled: March 26, 2020Date of Patent: October 12, 2021Assignee: GLOBALFOUNDRIES U.S. INC.Inventors: Nicholas A. Polomoff, Jae Kyu Cho, Mohamed A. Rabie, Andreas D. Stricker
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Publication number: 20210305172Abstract: Structures for an optical fiber groove and methods of forming a structure for an optical fiber groove. A photonics chip includes a substrate and an interconnect structure over the substrate. The photonics chip has a first exterior corner, a second exterior corner, and a side edge extending from the first exterior corner to the second exterior corner. The substrate includes a groove positioned along the side edge between the first exterior corner and the second exterior corner. The groove is arranged to intersect the side edge at a groove corner, and the interconnect structure includes metal structures adjacent to the first groove corner. The metal structures extend diagonally in the interconnect structure relative to the side edge of the photonics chip.Type: ApplicationFiled: March 26, 2020Publication date: September 30, 2021Inventors: Nicholas A. Polomoff, Jae Kyu Cho, Mohamed A. Rabie, Andreas D. Stricker
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Patent number: 10923397Abstract: A semiconductor device is provided that includes a substrate, an integrated circuit with a conductive member and a through-substrate-via (TSV) structure. The substrate includes a front surface and a back surface that is opposite the front surface. The integrated circuit with the conductive member is formed over the front surface of the substrate. The TSV structure having vertical sidewalls is formed in the back surface of the substrate connecting with the conductive member. The TSV structure includes a tapered first insulation layer, a conformal conductive layer and a second insulation layer, with the conformal conductive layer positioned between the first and second insulation layers. The conformal conductive layer is electrically connected to the conductive member.Type: GrantFiled: November 29, 2018Date of Patent: February 16, 2021Assignee: GLOBALFOUNDRIES Inc.Inventors: Mohamed A. Rabie, Md Sayed Kaysar Bin Rahim
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Publication number: 20200176312Abstract: A semiconductor device is provided that includes a substrate, an integrated circuit with a conductive member and a through-substrate-via (TSV) structure. The substrate includes a front surface and a back surface that is opposite the front surface. The integrated circuit with the conductive member is formed over the front surface of the substrate. The TSV structure having vertical sidewalls is formed in the back surface of the substrate connecting with the conductive member. The TSV structure includes a tapered first insulation layer, a conformal conductive layer and a second insulation layer, with the conformal conductive layer positioned between the first and second insulation layers. The conformal conductive layer is electrically connected to the conductive member.Type: ApplicationFiled: November 29, 2018Publication date: June 4, 2020Inventors: MOHAMED A. RABIE, MD SAYED KAYSAR BIN RAHIM
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Patent number: 10068859Abstract: A structure for arresting the propagation of cracks during the dicing of a semiconductor wafer into individual chips includes a monolithic metallic plate that traverses multiple dielectric layers peripheral to an active region of a chip. One or more metallic plates may be formed using lithography and electroplating techniques between the active device region and a peripheral kerf region, where each metallic plate includes a concave feature that faces the kerf region of the wafer.Type: GrantFiled: July 28, 2017Date of Patent: September 4, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Nicholas A. Polomoff, Mohamed Rabie, Victoria L. Calero Diaz Del Castillo, Danielle Degraw, Michael Hecker
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Publication number: 20170373019Abstract: A method for producing semiconductor devices including reinforcing metal tiles and the resulting semiconductor package are provided. Embodiments include forming one or more reinforcing metal tiles at corners of an upper portion of a metal stack of semiconductor die during manufacturing of the semiconductor die; and attaching the semiconductor die to a packaging substrate.Type: ApplicationFiled: June 27, 2016Publication date: December 28, 2017Inventor: Mohamed RABIE
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Publication number: 20170033061Abstract: Methods for creating effective noise reducing structures in an IC device to significantly reduce TSV-induced noise in an IC substrate of the IC device and the resulting device are disclosed. Embodiments include providing a plurality of circuits on an upper surface of an IC substrate; providing an active TSV in proximity to the circuits, wherein the TSV extends through the IC substrate; forming a noise reducing structure connected to a perimeter of a vertical segment of the active TSV; and connecting the noise reducing structure to an electrical ground node in common with the circuits.Type: ApplicationFiled: July 29, 2015Publication date: February 2, 2017Inventors: Mohamed RABIE, Premachandran CHIRAYARIKATHUVEEDU
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Publication number: 20150228555Abstract: Structures and methods of fabrication are provided with reduced or cancelled stress within the substrate of the structure adjacent to a through-substrate via. The fabrication method(s) includes: forming a structure with a through-substrate via (TSV) having a reduced device keep-out zone (KOZ) adjacent to the through-substrate via, the forming including: providing the through-substrate via within a substrate of the structure; and providing a stress-offset layer above the substrate selected and configured to provide a desired offset stress to reduce stress within the substrate caused by the presence of the through-substrate via within the substrate. In one embodiment, the stress-offset layer provides a desired compressive stress sufficient to reduce or eliminate tensile stress within the substrate due to the presence of the through-substrate via within the substrate.Type: ApplicationFiled: February 10, 2014Publication date: August 13, 2015Applicant: GLOBALFOUNDRIES INC.Inventors: Mohamed A. RABIE, Premachandran CHIRAYARIKATHUVEEDU, Mahadeva Iyer NATARAJAN