Patents by Inventor Mohamed Shaker Sarwary

Mohamed Shaker Sarwary has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130239080
    Abstract: Clock-domain crossing (CDC) verification for system on chip (SoC) integrated circuits (IC) can be time consuming and complex, especially as the size of the SoC and the complexity of the modules of which it comprises increase. A bottom-up verification process includes the replacement of a CDC verified module by an abstracted model of the module with constraints defined on the boundaries of the module. Performing the process in a hierarchic manner from bottom upwards allows for faster verification of modules higher in the hierarchy as at least portions thereof are replaced with the abstracted modules.
    Type: Application
    Filed: March 9, 2012
    Publication date: September 12, 2013
    Applicant: ATRENTA, INC.
    Inventors: Mohamed Shaker SARWARY, Maher MNEIMNEH, Paras Mal JAIN, Deepak AHUJA, Mohammad Homayoun MOVAHED-EZAZI
  • Publication number: 20120042294
    Abstract: Timing Constraints are crucial to meet timing requirements of an Integrated Circuit (IC). Timing exceptions are specified so that certain paths of the design of the IC are not timed as they are not relevant for the speed of the IC. If a path is specified as an exception but it is indeed a timing-relevant path then the design may functionally fail due to timing violations ignored by the timing analysis tools. It is therefore extremely important to ensure that all timing exceptions are correctly specified. The Hybrid Timing Exceptions Verification uses static verification as well as dynamic verification to effectively verify correctness of such timing exceptions. The solution pin-points the errors in the exceptions specification with very low number of false errors that would require significant designer inputs and time to manually waive them.
    Type: Application
    Filed: August 15, 2011
    Publication date: February 16, 2012
    Applicant: ATRENTA, INC.
    Inventor: Mohamed Shaker SARWARY
  • Patent number: 7506292
    Abstract: Unsynchronized clock-domain crossings in the design of integrated circuit are detected by searching for clock-crossing domains. For each clock-crossing that does not include an explicit synchronization cell, an analysis determines if the clock is stable crossing the domains.
    Type: Grant
    Filed: March 15, 2006
    Date of Patent: March 17, 2009
    Assignee: Atrenta, Inc.
    Inventors: Mohamed Shaker Sarwary, Mohammad Movahed Ezazi, Bernard Murphy
  • Patent number: 7073146
    Abstract: Unsynchronized clock-domain crossings in the design of integrated circuit are detected by searching for clock-crossing domains. For each clock-crossing that does not include an explicit synchronization cell, an analysis determines if the clock is stable crossing the domains.
    Type: Grant
    Filed: October 30, 2003
    Date of Patent: July 4, 2006
    Assignee: Atrenta Inc.
    Inventors: Mohamed Shaker Sarwary, Mohammad Movahed Ezazi, Bernard Murphy