Patents by Inventor Mohamed SOUBHI

Mohamed SOUBHI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240372640
    Abstract: The present document relates to a processing device and a method for performing time stamping of data at a high level of integrity such as ASIL (Automotive Safety Integrity Level) D. The processing device processes a data frame comprising data. Furthermore, upon reception of a trigger which is indicative of the processing of the data frame, the processing device captures a time stamp using a primary timer. Next, the processing device generates validation data based on the data frame and the time stamp. In addition, the processing device stores the validation data in conjunction with the data frame and the time stamp in a memory module.
    Type: Application
    Filed: April 15, 2024
    Publication date: November 7, 2024
    Inventors: Christian MARDMÖLLER, Mohamed SOUBHI, Stefan GELDREICH
  • Patent number: 12135624
    Abstract: A detection circuit for detecting faulty operation of an error correction code (ECC) decoder that is configured for diagnosing whether an error has occurred in input data to the ECC decoder, wherein the ECC decoder is further configured for outputting an error detection signal indicative of whether the error has been detected and potentially corrected by the ECC decoder and output data based on the input data, and wherein the detection circuit includes a first stage configured to generate a first check signal indicative of whether there is a mismatch between the input data and the output data of the ECC decoder, and a second stage configured to generate a second check signal indicative of whether faulty operation of the ECC decoder has been detected based on the first check signal and the error detection signal of the ECC decoder.
    Type: Grant
    Filed: December 14, 2022
    Date of Patent: November 5, 2024
    Assignee: Renesas Electronics Corporation
    Inventor: Mohamed Soubhi
  • Publication number: 20240202086
    Abstract: A detection circuit for detecting faulty operation of an error correction code (ECC) decoder that is configured for diagnosing whether an error has occurred in input data to the ECC decoder, wherein the ECC decoder is further configured for outputting an error detection signal indicative of whether the error has been detected and potentially corrected by the ECC decoder and output data based on the input data, and wherein the detection circuit includes a first stage configured to generate a first check signal indicative of whether there is a mismatch between the input data and the output data of the ECC decoder, and a second stage configured to generate a second check signal indicative of whether faulty operation of the ECC decoder has been detected based on the first check signal and the error detection signal of the ECC decoder.
    Type: Application
    Filed: December 14, 2022
    Publication date: June 20, 2024
    Applicant: Renesas Electronics Corporation
    Inventor: Mohamed SOUBHI
  • Publication number: 20230119255
    Abstract: An integrated circuit includes a safety processor and a secure computing module including a secure processor, first and second cryptographic units for encrypting and decrypting data, and first and second data transfer units for transferring data between a memory and the first and second cryptographic units respectively. The first cryptographic unit and the first data transfer unit provide a first cryptographic data handling system and the second cryptographic unit and the second data transfer unit provide a second cryptographic data handling system. The secure computing module includes selector circuitry for selectively coupling and uncoupling the first and second cryptographic units in response to control signals from a switch. In a first mode, the first and second cryptographic data handling systems are uncoupled and operable independently of each other. In a second mode, the first and second cryptographic data handling system are coupled and operable together to provide hardware redundancy.
    Type: Application
    Filed: October 7, 2022
    Publication date: April 20, 2023
    Applicant: Renesas Electronics Corporation
    Inventor: Mohamed SOUBHI