Abstract: Optical simulation can be performed employing a calibrated printing model, in which a unique phase transmission value is assigned to each type of sub-resolution assist features (SRAFs). The printing model can be calibrated employing a mask including multiple test patterns. Each test pattern is defined by a combination of a main feature, at least one SRAF applied to the main feature, and the geometrical relationship between the main feature and the at least one SRAF. Generation of the phase transmission values for each SRAF can be performed by fitting a printing model employing phase shift values and/or transmission values for SRAFs with measured printed feature dimensions as a function of defocus and/or with measured SRAF printing behavior on a printed photoresist layer. A properly calibrated printing model can predict the printed feature dimensions, shift in the best focus, and presence or absence of printed SRAFs.

Abstract: Optical simulation can be performed employing a calibrated printing model, in which a unique phase transmission value is assigned to each type of sub-resolution assist features (SRAFs). The printing model can be calibrated employing a mask including multiple test patterns. Each test pattern is defined by a combination of a main feature, at least one SRAF applied to the main feature, and the geometrical relationship between the main feature and the at least one SRAF. Generation of the phase transmission values for each SRAF can be performed by fitting a printing model employing phase shift values and/or transmission values for SRAFs with measured printed feature dimensions as a function of defocus and/or with measured SRAF printing behavior on a printed photoresist layer. A properly calibrated printing model can predict the printed feature dimensions, shift in the best focus, and presence or absence of printed SRAFs.

Abstract: A method, and computer program product and system for performing the method, is provided for designing a mask used in the manufacture of semiconductor integrated circuits, in which a model of the lithographic process is used during the mask design process. More particularly, the on-wafer process model is a function of optical image parameters that are calibrated using measurements from a test pattern. An uncertainty metric for the predicted response simulated by the on-wafer process model is computed for a given evaluation point of interest as a function of a distance metric between the collective optical image parameters simulated at the given evaluation point and the collective optical image parameters at the calibration data points. The uncertainty metric preferably is also a function of the sensitivity of the on-wafer process model response to changes in the optical image parameters.

Abstract: A method, and computer program product and system for performing the method, is provided for designing a mask used in the manufacture of semiconductor integrated circuits, in which a model of the lithographic process is used during the mask design process. More particularly, the on-wafer process model is a function of optical image parameters that are calibrated using measurements from a test pattern. An uncertainty metric for the predicted response simulated by the on-wafer process model is computed for a given evaluation point of interest as a function of a distance metric between the collective optical image parameters simulated at the given evaluation point and the collective optical image parameters at the calibration data points. The uncertainty metric preferably is also a function of the sensitivity of the on-wafer process model response to changes in the optical image parameters.

Abstract: A sub-circuit based extraction method which extracts a multi-finger MOS transistor directly as a sub-circuit is described. By adding three marking layers, the method provides the layout extracted netlist with a complete list of device geometric parameters corresponding to the device properties as presented in the sub-circuit model based schematic netlist. By performing a layout-versus-schematic comparison based on all geometric parameters extracted, the layout checking is performed in a complete and accurate way where each device parameter is checked against the corresponding design schematic. This complete and accurate geometric parameter comparison enhances the confidence level of the layout physical verification.

Abstract: A sub-circuit based extraction method which extracts a multi-finger MOS transistor directly as a sub-circuit is described. By adding three marking layers, the method provides the layout extracted netlist with a complete list of device geometric parameters corresponding to the device properties as presented in the sub-circuit model based schematic netlist. By performing a layout-versus-schematic comparison based on all geometric parameters extracted, the layout checking is performed in a complete and accurate way where each device parameter is checked against the corresponding design schematic. This complete and accurate geometric parameter comparison enhances the confidence level of the layout physical verification.