Abstract: An apparatus and a method to adjust a source voltage based on an operating voltage response are provided. The apparatus includes a circuit configured to change state from a first state to a second state comprising receiving an operating voltage from a power source through a power distribution network. The apparatus further includes a sensor configured to measure an operating voltage response to the circuit changing state to receiving the operating voltage. The apparatus further includes a control circuit configured to adjust a source voltage at the power source based on the operating voltage response measured by the sensor. The method includes changing a state to receiving an operating voltage from a power source through a power distribution network, measuring an operating voltage response to the changing state to receiving the operating voltage, and adjusting the source voltage at the power source based on the measured operating voltage response.

Abstract: A method including receiving an indication of a number of active processing units in a computer processor; in response to receiving the indication, determining an appropriate operating voltage margin for the computer processor; reducing an operating frequency of the active processing units in response to receiving the indication; adjusting a power supply to increase or decrease a voltage to the computer processor in accordance with the appropriate operating voltage margin; and increasing the operating frequency of the active processing units in response to an acknowledgment that the power supply has been adjusted.

Abstract: Systems and methods for power distribution network (PDN) droop/overshoot mitigation are provided. In certain embodiments, overshoot is mitigated by ramping down a frequency of a clock signal to a processor when the processor is switching clock frequencies and/or the processor is transitioning from an active mode to an idle mode. In certain embodiments, droop is mitigated by ramping up a frequency of a clock signal to a processor when the processor is switching clock frequencies and/or the processor is transitioning from an idle mode to an active mode.

Abstract: Systems and methods for dynamic clock and voltage scaling can switch integrated circuits between frequency-voltage modes with low latency. These systems include a resource power manager that can control a power management integrated circuit (PMIC), phase locked loops (PLLs), and clock dividers. The resource power manager controls transitions between frequency-voltage modes. The systems and methods provide dynamic clock and voltage scaling where the transitions between frequency-voltage modes are an atomic operation. Additionally, the resource power manager can control many modules, for example, clock dividers, in parallel. The invention can, due to lower latency between frequency-voltage modes, can provide improved system performance and reduced system power.

Abstract: Techniques for estimating state-dependent capacitance of a circuit are described herein. In one embodiment, a method for determining a circuit state for a circuit comprises determining a capacitance of the circuit for each one of a plurality of circuit states, and selecting one of the circuit states based on the determined capacitances.

Abstract: An apparatus and a method to adjust a source voltage based on an operating voltage response are provided. The apparatus includes a circuit configured to change state from a first state to a second state comprising receiving an operating voltage from a power source through a power distribution network. The apparatus further includes a sensor configured to measure an operating voltage response to the circuit changing state to receiving the operating voltage. The apparatus further includes a control circuit configured to adjust a source voltage at the power source based on the operating voltage response measured by the sensor. The method includes changing a state to receiving an operating voltage from a power source through a power distribution network, measuring an operating voltage response to the changing state to receiving the operating voltage, and adjusting the source voltage at the power source based on the measured operating voltage response.

Abstract: A method including receiving an indication of a number of active processing units in a computer processor; in response to receiving the indication, determining an appropriate operating voltage margin for the computer processor; reducing an operating frequency of the active processing units in response to receiving the indication; adjusting a power supply to increase or decrease a voltage to the computer processor in accordance with the appropriate operating voltage margin; and increasing the operating frequency of the active processing units in response to an acknowledgment that the power supply has been adjusted.

Abstract: Systems and methods for power distribution network (PDN) droop/overshoot mitigation are provided. In certain embodiments, overshoot is mitigated by ramping down a frequency of a clock signal to a processor when the processor is switching clock frequencies and/or the processor is transitioning from an active mode to an idle mode. In certain embodiments, droop is mitigated by ramping up a frequency of a clock signal to a processor when the processor is switching clock frequencies and/or the processor is transitioning from an idle mode to an active mode.

Abstract: An integrated circuit compensates for circuit aging by measuring the aging with an aging sensor and controlling a supply voltage based on the measured aging. The operating environment for the aging sensor can be set to reduce impacts of non-aging effects on the measured aging. For example, the operating environment can use a temperature inversion voltage. An initial aging measurement value which is the difference between an initial aged measurement and an initial unaged measurement can be stored on the integrated circuit. A core power reduction controller can use the measured aging and the stored initial aging measurement value to update a performance-sensor target value and then perform adaptive voltage scaling using the using the updated performance-sensor target value.

Abstract: An apparatus is provided. The apparatus includes a plurality of counters configured to count electrical activity switching events of cores, a first circuit configured to predict a temperature at a location based on counts of at least one of the plurality of counters, and a second circuit configured to schedule a thermal mitigation function based on the predicted temperature. A method for scheduling thermal mitigation functions is provided. The method includes counting electrical activity switching events, predicting a temperature at a location based on the counting of the electrical activity switching events, and scheduling a thermal mitigation function based on the predicted temperature. Another apparatus is provided. The apparatus includes means for counting electrical activity switching events, means for predicting a temperature at a location based on a count of the electrical activity switching events, and means for scheduling a thermal mitigation function based on the predicted temperature.

Abstract: Systems and methods for performing thermal simulations of a system are disclosed herein in. In one embodiment, a computer-implemented method for thermal simulation comprises determining a leakage power profile for a circuit in the system, adding the leakage power profile to a dynamic power profile of the circuit to obtain a combined power profile, and convolving the combined power profile with an impulse response to obtain a thermal response at a location on the system.

Abstract: Systems and methods for dynamic clock and voltage scaling can switch integrated circuits between frequency-voltage modes with low latency. These systems include a resource power manager that can control a power management integrated circuit (PMIC), phase locked loops (PLLs), and clock dividers. The resource power manager controls transitions between frequency-voltage modes. The systems and methods provide dynamic clock and voltage scaling where the transitions between frequency-voltage modes are an atomic operation. Additionally, the resource power manager can control many modules, for example, clock dividers, in parallel. The invention can, due to lower latency between frequency-voltage modes, can provide improved system performance and reduced system power.

Abstract: Techniques for estimating state-dependent capacitance of a circuit are described herein. In one embodiment, a method for determining a circuit state for a circuit comprises determining a capacitance of the circuit for each one of a plurality of circuit states, and selecting one of the circuit states based on the determined capacitances.