Abstract: A request hint is issued prior to or while identifying whether requested data and/or one or more instructions are in a first memory. A second memory is accessed to fetch data and/or one or more instructions in response to the request hint. The data and/or instruction(s) accessed from the second memory are stored in a buffer. If the requested data and/or instruction(s) are not in the first memory, the data and/or instruction(s) are returned from the buffer.

Abstract: An efficient way to determine which objects in a 3D image are to be displayed and which are not because they are obscured by other displayed objects. Displayable elements are assigned depth values defining their relative perceived nearness to the viewer of the image. A comparison of depth values determines which elements are to be displayed and which are not to be displayed because they are obscured by displayed elements. Rather than comparing the depth value of every pixel in a displayable object to determine whether it is to be displayed, the invention compares groups of pixels defined by spans. Minimum and maximum depth values are determined for each span so that depth variations within a span can be accommodated. Masks are used when only partial spans are to be considered because some pixels in a span are outside the pixel boundaries being considered in a particular comparison.

Abstract: An efficient way to determine which objects in a 3D image are to be displayed and which are not because they are obscured by other displayed objects. Displayable elements are assigned depth values defining their relative perceived nearness to the viewer of the image. A comparison of depth values determines which elements are to be displayed and which are not to be displayed because they are obscured by displayed elements. Rather than comparing the depth value of every pixel in a displayable object to determine whether it is to be displayed, the invention compares groups of pixels defined by spans. Minimum and maximum depth values are determined for each span so that depth variations within a span can be accommodated. Masks are used when only partial spans are to be considered because some pixels in a span are outside the pixel boundaries being considered in a particular comparison.

Abstract: A prefetcher to prefetch data for an instruction based on the distance between cache misses caused by the instruction. In an embodiment, the prefetcher includes a memory to store a prefetch table that contains one or more entries that include the distance between cache misses caused by an instruction. In a further embodiment, the addresses of data elements prefetched are determined based on the distance between cache misses recorded in the prefetch table for the instruction.

Abstract: A processor includes a cache that has a lines to store data. The processor also includes prefetch bits each of which is associated with one of the cache lines. The processor further includes a prefetch manager that calculates prefetch data as if a cache miss occurred whenever a cache request results in a cache hit to a cache line that is associated with a prefetch bit that is set. In a further embodiment, the prefetch manager prefetches data into the cache based on the distance between cache misses for an instruction.

Abstract: A method and apparatus that adds each one of multiple elements of a packed data together to produce a result. According to one such a method and apparatus, each of a first set of portions of partial products is produced using a first set of partial product selectors in a multiplier, each of the first set of portions of the partial products being zero. Each of the multiple elements is inserted into one of a second set of portions of the partial products using a second set of partial product selectors, each of the second set of portions of the partial products being aligned. Each of the multiple elements are added together to produce the result including a field having the sum of the multiple elements.

Abstract: A method and apparatus that adds each one of multiple elements of a packed data together to produce a result. According to one such a method and apparatus, each of a first set of portions of partial products is produced using a first set of partial product selectors in a multiplier, each of the first set of portions of the partial products being zero. Each of the multiple elements is inserted into one of a second set of portions of the partial products using a second set of partial product selectors, each of the second set of portions of the partial products being aligned. Each of the multiple elements are added together to produce the result including a field having the sum of the multiple elements.

Abstract: A floating point arithmetic apparatus for converting numbers between an integer format and a floating point format, wherein a conversion operation requires a greater data path width than a conversion operation. The apparatus comprises right shift circuitry that receives a number in the floating point format, wherein the right shift circuitry includes additional register positions to accommodate a shift beyond a data path width required by an arithmetic operation.

Abstract: A 3x adder for adding 2a to a, where a is a binary number, the binary numbers 2a and a partitioned so that 2a=(xk . . . x0) and a=(yk . . . y0)where xi and yi have the same size for each i=0, 1, . . . , k, where the 3x adder provides the group generate terms for the sums xi+yi, i=0, 1, . . . , k, according to Boolean expressions, where for any sum xi+yi where xi and yi each have size n1+1, the number of Boolean variables in the product terms in the Boolean expression for the group generate terms of xi+yi do not exceed j+1, where j is the largest integer not exceeding ni/2.

Abstract: A method and apparatus for computing a Packed Absolute Differences. According to one such method and apparatus, a third packed data having a third plurality of elements and the plurality of sign bits is produced, each of the third plurality of elements and the plurality of sign bits being computed by subtracting one of a first plurality of elements of a first packed data from a corresponding one of a second plurality of elements of a second packed data. The third plurality of elements and the plurality of sign bits are stored.

Abstract: A method and apparatus are provided for executing scalar packed data instructions. According to one aspect of the invention, a processor includes a plurality of registers, a register renaming unit coupled to the plurality of registers, a decoder coupled to the register renaming unit, and a partial-width execution unit coupled to the decoder. The register renaming unit provides an architectural register file to store packed data operands each of which include a plurality of data elements. The decoder is configured to decode a first and second set of instructions that each specify one or more registers in the architectural register file. Each of the instructions in the first set of instructions specify operations to be performed on all of the data elements stored in the one or more specified registers. In contrast, each of the instructions in the second set of instructions specify operations to be performed on only a subset of the data element stored in the one or more specified registers.

Abstract: A method and apparatus are provided for executing scalar packed data instructions. According to one aspect of the invention, a processor includes a plurality of registers, a register renaming unit coupled to the plurality of registers, and a decoder coupled to the register renaming unit. The register renaming unit provides an architectural register file to store packed data operands each of which include a plurality of data elements. The decoder is configured to decode a first and second set of instructions (e.g., a set of full-width packed data instructions and a set of partial-width packed data instructions) that each specify one or more registers in the architectural register file. Each of the instructions in the first set of instructions specify operations to be performed on all of the data elements stored in the one or more specified registers.