Abstract: A memory device includes a memory array powered between a virtual supply and virtual ground nodes. A dummy memory array is powered between first and second nodes. A virtual supply generation circuit generates a virtual supply voltage at the virtual supply node as a function of a first control voltage. A virtual ground generation circuit generates a virtual ground at the virtual ground node as a function of a second control voltage. A first control voltage generation circuit coupled between the first node and a power supply voltage generates the first control voltage as tracking retention noise margin (RNM) of the memory array, the first control voltage falling as the RNM decreases. A second control voltage generation circuit coupled between the second node and ground generates the second control voltage as tracking RNM of the memory array, the second control voltage rising as the RNM decreases.

Abstract: A memory device includes a memory array powered between a virtual supply and virtual ground nodes. A dummy memory array is powered between first and second nodes. A virtual supply generation circuit generates a virtual supply voltage at the virtual supply node as a function of a first control voltage. A virtual ground generation circuit generates a virtual ground at the virtual ground node as a function of a second control voltage. A first control voltage generation circuit coupled between the first node and a power supply voltage generates the first control voltage as tracking retention noise margin (RNM) of the memory array, the first control voltage falling as the RNM decreases. A second control voltage generation circuit coupled between the second node and ground generates the second control voltage as tracking RNM of the memory array, the second control voltage rising as the RNM decreases.

Abstract: A wordline coupled to a memory cell is selected in connection with performing a read/write operation at the memory cell. A wordline signal is asserted on the selected wordline. The assertion of the wordline signal has a leading edge and a trailing edge and, between the leading edge and trailing edge, a series of wordline underdrive pulses. Each wordline underdrive pulse causes a wordline voltage to fall from a first voltage level to a second voltage level and then rise from the second voltage level to the first voltage level. The first and second voltage levels are both greater than a ground voltage of the memory cell.