Abstract: In some implementations, a vertical-cavity surface-emitting laser (VCSEL) array may comprise a plurality of channels, a plurality of traces, and a plurality of emitters. A channel, of the plurality of channels, may include a set of emitters, of the plurality of emitters, arranged in a row of emitters. The channel may include a trace, of the plurality of traces, that has a trace width that is tapered along a length of the trace. Numerous other aspects are provided.

Abstract: A VCSEL array may include a semiconductor substrate and a plurality of emitters on the substrate that conforms to an emitter pattern. The emitter pattern may be oriented at a non-zero angle to an edge of the substrate and may comprise two or more unit cells arranged to form the emitter pattern. Each unit cell, of the two or more unit cells, may include a same number of emitters, and the two or more unit cells may be arranged to cause a measurement of misalignment associated with two adjacent unit cells, of the two or more unit cells, to satisfy a misalignment threshold.

Abstract: In some implementations, a surface emitting laser may have an emitter design with a short oxidation length and/or a large number of trenches. For example, the surface emitting laser may comprise a metallization layer comprising multiple extended portions extending outwards from a circumference of an inner ring portion, and multiple tabs extending laterally from the multiple extended portions in a partial ring shape. The surface emitting laser may further comprise multiple via openings connecting the metallization layer to a plating metal, where each via opening is positioned over a corresponding tab, of the multiple tabs. The surface emitting laser may comprise multiple oxidation trenches that are each formed in an angular gap between a pair of extended portions, of the multiple extended portions, such that the multiple tabs and the multiple via openings are exclusively outside outer radii of the multiple oxidation trenches.

Abstract: An optical chip may include a vertical-cavity surface-emitting laser (VCSEL) structure. The optical chip may include a capacitor over at least a portion of an active layer of the VCSEL structure that is outside of an active region of the VCSEL structure. The capacitor may include a first metal layer over the portion of the active layer, a dielectric layer on the first metal layer, and a second metal layer on the dielectric layer. The optical chip may include an isolation region between a substrate of the VCSEL and a portion of the capacitor outside of the VCSEL.

Abstract: In some implementations, a surface emitting laser may have an emitter design with a short oxidation length and/or a large number of trenches. For example, the surface emitting laser may comprise a metallization layer comprising multiple extended portions extending outwards from a circumference of an inner ring portion, and multiple tabs extending laterally from the multiple extended portions in a partial ring shape. The surface emitting laser may further comprise multiple via openings connecting the metallization layer to a plating metal, where each via opening is positioned over a corresponding tab, of the multiple tabs. The surface emitting laser may comprise multiple oxidation trenches that are each formed in an angular gap between a pair of extended portions, of the multiple extended portions, such that the multiple tabs and the multiple via openings are exclusively outside outer radii of the multiple oxidation trenches.

Abstract: In some implementations, a vertical-cavity surface-emitting laser (VCSEL) array may comprise a plurality of channels, a plurality of traces, and a plurality of emitters. A channel, of the plurality of channels, may include a set of emitters, of the plurality of emitters, arranged in a row of emitters. The channel may include a trace, of the plurality of traces, that has a trace width that is tapered along a length of the trace. Numerous other aspects are provided.

Abstract: A VCSEL array may include a semiconductor substrate and a plurality of emitters on the substrate that conforms to an emitter pattern. The emitter pattern may be oriented at a non-zero angle to an edge of the substrate and may comprise two or more unit cells arranged to form the emitter pattern. Each unit cell, of the two or more unit cells, may include a same number of emitters, and the two or more unit cells may be arranged to cause a measurement of misalignment associated with two adjacent unit cells, of the two or more unit cells, to satisfy a misalignment threshold.