Abstract: An integrated circuitry (IC) device for a memory device includes driver circuitry, selection circuitry, clock generation circuitry, and self-time path circuitry. The driver circuitry generates a plurality of driver circuitry outputs. The selection circuitry selects one of the plurality of driver circuitry outputs based on a plurality of enable signals. The clock generation circuitry receives the selected one of the plurality of driver circuitry outputs from the selection circuitry, and generates a clock signal based on at least the selected one of the plurality of driver circuitry outputs from the selection circuitry. The self-time path circuitry of a memory receives the clock signal and generates a reset signal based on the clock signal. The plurality of driver circuitry outputs and the clock signal are based on the reset signal, and the self-time path circuitry corresponds to one or more columns of a memory bank.

Abstract: Examples described herein generally relate to devices that include a pulsed flip-flop capable of being implemented across multiple voltage domains. In an example, a device includes a pulsed flip-flop. The pulsed flip-flop includes a master circuit and a slave circuit sequentially connected to the master circuit. The master circuit includes a pre-charge input circuit and a first latch. A first node is connected between the pre-charge input circuit and the first latch. The slave circuit includes a resolving circuit and a second latch. The first node is connected to an input node of the resolving circuit. A second node is connected between the resolving circuit and the second latch. The resolving circuit is configured to selectively (i) pull up or pull down a voltage of the second node and (ii) be disabled.