Abstract: A radar signal processing system with a self-interference cancelling function includes an analog front end (AFE) processor, an analog to digital converter (ADC), an adaptive interference canceller (AIC), and a digital to analog converter (DAC). The AFE processor receives an original input signal and generates an analog input signal. The ADC converts the analog input signal to a digital input signal. The AIC generates a digital interference signal digital interference signal by performing an adaptive interference cancellation process according to the digital input signal. The DAC converts the digital interference signal to an analog interference signal. Finally, the analog interference signal is fed back to the AFE and cancelled from the original input signal in the AFE processor while performing the front end process, reducing the interference of the static interference from the leaking of a close-by transmitter during the front end process.

Abstract: A radar signal processing system with a self-interference cancelling function includes an analog front end (AFE) processor, an analog to digital converter (ADC), an adaptive interference canceller (AIC), and a digital to analog converter (DAC). The AFE processor receives an original input signal and generates an analog input signal. The ADC converts the analog input signal to a digital input signal. The AIC generates a digital interference signal digital interference signal by performing an adaptive interference cancellation process according to the digital input signal. The DAC converts the digital interference signal to an analog interference signal. Finally, the analog interference signal is fed back to the AFE and cancelled from the original input signal in the AFE processor while performing the front end process, reducing the interference of the static interference from the leaking of a close-by transmitter during the front end process.

Abstract: The present invention provides systems and methods to detect when hard decisions change for bit nodes of one or more layers of a layered LDPC decoder and to update accumulated partial syndrome calculations for those layers. As hard decisions of bit nodes are generated, they are compared with their previous values. If the hard decisions change, partial syndrome calculations are accumulated and updated for the layers having non-zero elements in one or more columns of the parity check matrix corresponding to the bit nodes of the changed hard decisions. If the hard decisions for the bit nodes are unchanged, the partial syndrome calculations for the corresponding layers are not updated. Changes to hard decisions of codewords are tracked and partial syndromes are flipped for the layers of the columns of the parity check matrix corresponding to the bit nodes of the changed hard decisions.

Abstract: The present invention provides systems and methods to detect when hard decisions change for bit nodes of one or more layers of a layered LDPC decoder and to update accumulated partial syndrome calculations for those layers. As hard decisions of bit nodes are generated, they are compared with their previous values. If the hard decisions change, partial syndrome calculations are accumulated and updated for the layers having non-zero elements in one or more columns of the parity check matrix corresponding to the bit nodes of the changed hard decisions. If the hard decisions for the bit nodes are unchanged, the partial syndrome calculations for the corresponding layers are not updated. Changes to hard decisions of codewords are tracked and partial syndromes are flipped for the layers of the columns of the parity check matrix corresponding to the bit nodes of the changed hard decisions.