Patents by Inventor Mohammad Elbadry
Mohammad Elbadry has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12199608Abstract: An apparatus, a system, and a communication device. The apparatus includes a substrate and a circuit formed on the substrate. The circuit includes a first transformer having first input nodes and first output nodes. The circuit further includes a second transformer having second input nodes and second output nodes. The first input nodes of the first transformer and the second input nodes of the second transformer are connected. At least one first output node of the first output nodes of the first transformer and at least one second output node of the second output nodes of the second transformer are connected. The circuit further includes a first capacitor connected to one of the first output nodes of the first transformer and to one of the second output nodes of the second transformer. The first capacitor is connected to a first ground.Type: GrantFiled: October 10, 2022Date of Patent: January 14, 2025Assignee: Avago Technologies International Sales Pte. LimitedInventors: Alireza Nilchi, Adesh Garg, Mohammad Elbadry, Ahmed Elkholy, Jun Cao
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Publication number: 20240120905Abstract: An apparatus, a system, and a communication device. The apparatus includes a substrate and a circuit formed on the substrate. The circuit includes a first transformer having first input nodes and first output nodes. The circuit further includes a second transformer having second input nodes and second output nodes. The first input nodes of the first transformer and the second input nodes of the second transformer are connected. At least one first output node of the first output nodes of the first transformer and at least one second output node of the second output nodes of the second transformer are connected. The circuit further includes a first capacitor connected to one of the first output nodes of the first transformer and to one of the second output nodes of the second transformer. The first capacitor is connected to a first ground.Type: ApplicationFiled: October 10, 2022Publication date: April 11, 2024Inventors: Alireza Nilchi, Adesh Garg, Mohammad Elbadry, Ahmed Elkholy, Jun Cao
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Patent number: 10547297Abstract: A duty cycle correction circuit includes a charge pump and a controller. The charge pump includes a current source, a first output, and a second output. The charge pump routes current from the current source to the first output during a positive portion of a clock, and routes current from the current source to the second output during a negative portion of the clock. The controller compares charge accumulated from the first output to charge accumulated from the second output over a plurality of clock cycles to determine which of the positive portion of the clock and the negative portion of the clock is longer. The controller also generates a digital value that indicates an amount of adjustment to apply to a duty cycle of the clock based on which of the positive portion of the clock and the negative portion of the clock is longer.Type: GrantFiled: May 13, 2019Date of Patent: January 28, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Mohammad Elbadry, Robert Floyd Payne, Gerd Schuppener
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Publication number: 20190267979Abstract: A duty cycle correction circuit includes a charge pump and a controller. The charge pump includes a current source, a first output, and a second output. The charge pump routes current from the current source to the first output during a positive portion of a clock, and routes current from the current source to the second output during a negative portion of the clock. The controller compares charge accumulated from the first output to charge accumulated from the second output over a plurality of clock cycles to determine which of the positive portion of the clock and the negative portion of the clock is longer. The controller also generates a digital value that indicates an amount of adjustment to apply to a duty cycle of the clock based on which of the positive portion of the clock and the negative portion of the clock is longer.Type: ApplicationFiled: May 13, 2019Publication date: August 29, 2019Inventors: Mohammad Elbadry, Robert Floyd Payne, Gerd Schuppener
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Patent number: 10291242Abstract: Certain aspects of the present disclosure generally relate to techniques and circuits for phase correction, or at least adjustment, of multiple local-oscillator (LO) signals. For example, certain aspects provide an apparatus for phase adjustment. The apparatus generally includes a phase-locked loop (PLL), at least one frequency divider coupled to an output of the PLL, the at least one first frequency divider being external to the PLL, a phase adjustment circuit having an input coupled to an output of the frequency divider, and at least one mixer having an input coupled to at least one output of the phase adjustment circuit.Type: GrantFiled: May 30, 2018Date of Patent: May 14, 2019Assignee: QUALCOMM IncorporatedInventors: Mohammad Elbadry, Marco Zanuso, Tsai-Pi Hung, Francesco Gatta, Yunliang Zhu
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Patent number: 10291218Abstract: A duty cycle correction circuit includes a charge pump and a controller. The charge pump includes a current source, a first output, and a second output. The charge pump routes current from the current source to the first output during a positive portion of a clock, and routes current from the current source to the second output during a negative portion of the clock. The controller compares charge accumulated from the first output to charge accumulated from the second output over a plurality of clock cycles to determine which of the positive portion of the clock and the negative portion of the clock is longer. The controller also generates a digital value that indicates an amount of adjustment to apply to a duty cycle of the clock based on which of the positive portion of the clock and the negative portion of the clock is longer.Type: GrantFiled: June 29, 2018Date of Patent: May 14, 2019Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Mohammad Elbadry, Robert Floyd Payne, Gerd Schuppener
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Publication number: 20180309431Abstract: A duty cycle correction circuit includes a charge pump and a controller. The charge pump includes a current source, a first output, and a second output. The charge pump routes current from the current source to the first output during a positive portion of a clock, and routes current from the current source to the second output during a negative portion of the clock. The controller compares charge accumulated from the first output to charge accumulated from the second output over a plurality of clock cycles to determine which of the positive portion of the clock and the negative portion of the clock is longer. The controller also generates a digital value that indicates an amount of adjustment to apply to a duty cycle of the clock based on which of the positive portion of the clock and the negative portion of the clock is longer.Type: ApplicationFiled: June 29, 2018Publication date: October 25, 2018Inventors: Mohammad Elbadry, Robert Floyd Payne, Gerd Schuppener
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Patent number: 10033365Abstract: A duty cycle correction circuit includes a charge pump and a controller. The charge pump includes a current source, a first output, and a second output. The charge pump routes current from the current source to the first output during a positive portion of a clock, and routes current from the current source to the second output during a negative portion of the clock. The controller compares charge accumulated from the first output to charge accumulated from the second output over a plurality of clock cycles to determine which of the positive portion of the clock and the negative portion of the clock is longer. The controller also generates a digital value that indicates an amount of adjustment to apply to a duty cycle of the clock based on which of the positive portion of the clock and the negative portion of the clock is longer.Type: GrantFiled: May 18, 2017Date of Patent: July 24, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Mohammad Elbadry, Robert Floyd Payne, Gerd Schuppener
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Patent number: 9893875Abstract: A phase discontinuity mitigation implementation within a phased lock loop (PLL) improves throughput of a radio access technology. The throughput is improved by maintaining a phase of the PLL while powering off some devices of the PLL, such as a local oscillator (LO) frequency divider. In one instance, when the PLL is powered down, one or more portions of a delta sigma modulator for the PLL are clocked with a reference clock for the PLL. This implementation maintains phase continuity when the first phase lock loop turns back on.Type: GrantFiled: September 20, 2016Date of Patent: February 13, 2018Assignee: QUALCOMM IncorporatedInventors: Marco Zanuso, Mohammad Elbadry, Tsai-Pi Hung, Ravi Sridhara, Francesco Gatta, Jingcheng Zhuang
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Publication number: 20170338940Abstract: A phase discontinuity mitigation implementation within a phased lock loop (PLL) improves throughput of a radio access technology. The throughput is improved by maintaining a phase of the PLL while powering off some devices of the PLL, such as a local oscillator (LO) frequency divider. In one instance, when the PLL is powered down, one or more portions of a delta sigma modulator for the PLL are clocked with a reference clock for the PLL. This implementation maintains phase continuity when the first phase lock loop turns back on.Type: ApplicationFiled: September 20, 2016Publication date: November 23, 2017Inventors: Marco ZANUSO, Mohammad ELBADRY, Tsai-Pi HUNG, Ravi SRIDHARA, Francesco GATTA, Jingcheng ZHUANG
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Patent number: 9780768Abstract: A duty cycle correction circuit includes a charge pump and a controller. The charge pump includes a current source, a first output, and a second output. The charge pump routes current from the current source to the first output during a positive portion of a clock, and routes current from the current source to the second output during a negative portion of the clock. The controller compares charge accumulated from the first output to charge accumulated from the second output over a plurality of clock cycles to determine which of the positive portion of the clock and the negative portion of the clock is longer. The controller also generates a digital value that indicates an amount of adjustment to apply to a duty cycle of the clock based on which of the positive portion of the clock and the negative portion of the clock is longer.Type: GrantFiled: October 30, 2015Date of Patent: October 3, 2017Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Mohammad Elbadry, Robert Floyd Payne, Gerd Schuppener
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Publication number: 20170257087Abstract: A duty cycle correction circuit includes a charge pump and a controller. The charge pump includes a current source, a first output, and a second output. The charge pump routes current from the current source to the first output during a positive portion of a clock, and routes current from the current source to the second output during a negative portion of the clock. The controller compares charge accumulated from the first output to charge accumulated from the second output over a plurality of clock cycles to determine which of the positive portion of the clock and the negative portion of the clock is longer. The controller also generates a digital value that indicates an amount of adjustment to apply to a duty cycle of the clock based on which of the positive portion of the clock and the negative portion of the clock is longer.Type: ApplicationFiled: May 18, 2017Publication date: September 7, 2017Inventors: Mohammad Elbadry, Robert Floyd Payne, Gerd Schuppener
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Patent number: 9692403Abstract: A clock generator includes a duty cycle correction circuit. The duty cycle correction circuit includes a duty cycle detector. The duty cycle detector, includes a first programmable delay element and a controller. The first programmable delay element is configured to delay a clock signal. The controller is configured to vary an amount of delay applied to the clock signal by the first programmable delay element, and to apply a delayed version of the clock signal, provided by the first programmable delay element, to locate an edge of a different version of the clock signal and measure time during which the different version of the clock is high. The controller is also configured to generate a digital value that indicates an amount of adjustment to apply to a duty cycle of the clock signal based on measured time during which the different version of the clock is high.Type: GrantFiled: October 30, 2015Date of Patent: June 27, 2017Assignee: TEXAS INSTRUMENTS INCORPORATEDInventor: Mohammad Elbadry
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Publication number: 20170126219Abstract: A duty cycle correction circuit includes a charge pump and a controller. The charge pump includes a current source, a first output, and a second output. The charge pump routes current from the current source to the first output during a positive portion of a clock, and routes current from the current source to the second output during a negative portion of the clock. The controller compares charge accumulated from the first output to charge accumulated from the second output over a plurality of clock cycles to determine which of the positive portion of the clock and the negative portion of the clock is longer. The controller also generates a digital value that indicates an amount of adjustment to apply to a duty cycle of the clock based on which of the positive portion of the clock and the negative portion of the clock is longer.Type: ApplicationFiled: October 30, 2015Publication date: May 4, 2017Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Mohammad ELBADRY, Robert Floyd PAYNE, Gerd Schuppener
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Publication number: 20170126220Abstract: A clock generator includes a duty cycle correction circuit. The duty cycle correction circuit includes a duty cycle detector. The duty cycle detector, includes a first programmable delay element and a controller. The first programmable delay element is configured to delay a clock signal. The controller is configured to vary an amount of delay applied to the clock signal by the first programmable delay element, and to apply a delayed version of the clock signal, provided by the first programmable delay element, to locate an edge of a different version of the clock signal and measure time during which the different version of the clock is high. The controller is also configured to generate a digital value that indicates an amount of adjustment to apply to a duty cycle of the clock signal based on measured time during which the different version of the clock is high.Type: ApplicationFiled: October 30, 2015Publication date: May 4, 2017Applicant: TEXAS INSTRUMENTS INCORPORATEDInventor: Mohammad ELBADRY
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Patent number: 9467178Abstract: A linear transform can be performed using a passive analog multi-stage charge re-use linear transform circuit. The passive analog multi-stage charge re-use linear transform circuit transforms an input analog circuit to generate a transformed analog output signal. The passive analog multi-stage charge re-use linear transform circuit may be included in a software defined radio (SDR), where the transformed analog output signal may be output to an analog-to-digital converter (ADC) of the SDR device so as to enable the ADC to perform wideband spectrum sensing. The passive analog multi-stage charge re-use linear transform circuit may also be included in a beamforming device so as to enable the device to perform spectral shifting and spatial shifting of signals. This passive analog multi-stage charge re-use linear transform circuit may promote reduced power consumption in comparison to other circuits while also supporting wideband applications at high sampling rates.Type: GrantFiled: March 19, 2014Date of Patent: October 11, 2016Assignee: Regents of the University of MinnesotaInventors: Ramesh Harjani, Bodhisatwa Sadhu, Martin D. Sturm, Sachin Kalia, Satwik Patnaik, Mohammad Elbadry
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Publication number: 20150280752Abstract: A linear transform can be performed using a passive analog multi-stage charge re-use linear transform circuit. The passive analog multi-stage charge re-use linear transform circuit transforms an input analog circuit to generate a transformed analog output signal. The passive analog multi-stage charge re-use linear transform circuit may be included in a software defined radio (SDR), where the transformed analog output signal may be output to an analog-to-digital converter (ADC) of the SDR device so as to enable the ADC to perform wideband spectrum sensing. The passive analog multi-stage charge re-use linear transform circuit may also be included in a beamforming device so as to enable the device to perform spectral shifting and spatial shifting of signals. This passive analog multi-stage charge re-use linear transform circuit may promote reduced power consumption in comparison to other circuits while also supporting wideband applications at high sampling rates.Type: ApplicationFiled: March 19, 2014Publication date: October 1, 2015Applicant: Regents of the University of MinnesotaInventors: Ramesh Harjani, Bodhisatwa Sadhu, Martin D. Sturm, Sachin Kalia, Satwik Patnaik, Mohammad Elbadry