Abstract: Embodiments in accordance with the present invention relate to techniques which avoid the problems of deformation in the shape of a solder connection in a flip chip package, resulting from solder reflow. In one embodiment, a solder-repellent surface is created adjacent to the solder to constrain the reflow and thereby maintain the vertical profile of the solder. Examples of such a solder-repellent surface include an oxide (such as Brown Oxide) of the lead frame, or a tape (such as Kapton) which is used as a dam bar to control/constrain the solder flow on the leads prior to the encapsulation step. In another embodiment, the solder connection may be formed from at least two components. The first component may reflow at high temperatures to provide the necessary adhesion between solder ball and the die, with the second component reflowing at a lower temperature to provide the necessary adhesion between the solder ball and the leads.

Abstract: Embodiments of the present invention relate to the use of stamping to form features on a lead frame of a semiconductor device package. In one embodiment, portions of the lead frame such as pins are moved out of the horizontal plane of a diepad by stamping. In certain embodiments, indentations or a complex cross-sectional profile, such as chamfered, may be imparted to portions of the pins and/or diepad by stamping. The complexity offered by such a stamped cross-sectional profile serves to enhance mechanical interlocking of the lead frame within the plastic molding of the package body. Other techniques such as selective electroplating and/or formation of a brown oxide guard band to limit spreading of adhesive material during die attach, may be employed alone or in combination to facilitate fabrication of a package having such stamped features.

Abstract: A method of fabricating a large area, multi-element contactor. A segmented contactor is provided for testing semiconductor devices on a wafer that comprises a plurality of contactor units mounted to a substrate. The contactor units are formed, tested, and assembled to a backing substrate. The contactor units may include leads extending laterally for connection to an external instrument such as a burn-in board. The contactor units include conductive areas such as pads that are placed into contact with conductive terminals on devices under test.

Abstract: A method of fabricating a large area, multi-element contactor. A segmented contactor is provided for testing semiconductor devices on a wafer that comprises a plurality of contactor units mounted to a substrate. The contactor units are formed, tested, and assembled to a backing substrate. The contactor units may include leads extending laterally for connection to an external instrument such as a burn-in board. The contactor units include conductive areas such as pads that are placed into contact with conductive terminals on devices under test.

Abstract: Embodiments of the present invention relate to the use of stamping to form features on a lead frame of a semiconductor device package. In one embodiment, portions of the lead frame such as pins are moved out of the horizontal plane of a diepad by stamping. In certain embodiments, indentations or a complex cross-sectional profile, such as chamfered, may be imparted to portions of the pins and/or diepad by stamping. The complexity offered by such a stamped cross-sectional profile serves to enhance mechanical interlocking of the lead frame within the plastic molding of the package body. Other techniques such as selective electroplating and/or formation of a brown oxide guard band to limit spreading of adhesive material during die attach, may be employed alone or in combination to facilitate fabrication of a package having such stamped features.

Abstract: Embodiments of the present invention relate to the use of stamping to form features on a lead frame of a semiconductor device package. In one embodiment, portions of the lead frame such as pins are moved out of the horizontal plane of a diepad by stamping. In certain embodiments, indentations or a complex cross-sectional profile, such as chamfered, may be imparted to portions of the pins and/or diepad by stamping. The complexity offered by such a stamped cross-sectional profile serves to enhance mechanical interlocking of the lead frame within the plastic molding of the package body. Other techniques such as selective electroplating and/or formation of a brown oxide guard band to limit spreading of adhesive material during die attach, may be employed alone or in combination to facilitate fabrication of a package having such stamped features.

Abstract: Embodiments in accordance with the present invention relate to techniques which avoid the problems of deformation in the shape of a solder connection in a flip chip package, resulting from solder reflow. In one embodiment, a solder-repellent surface is created adjacent to the solder to constrain the reflow and thereby maintain the vertical profile of the solder. Examples of such a solder-repellent surface include an oxide (such as Brown Oxide) of the lead frame, or a tape (such as Kapton) which is used as a dam bar to control/constrain the solder flow on the leads prior to the encapsulation step. In another embodiment, the solder connection may be formed from at least two components. The first component may reflow at high temperatures to provide the necessary adhesion between solder ball and the die, with the second component reflowing at a lower temperature to provide the necessary adhesion between the solder ball and the leads.

Abstract: Embodiments in accordance with the present invention relate to techniques which avoid the problems of deformation in the shape of a solder connection in a flip chip package, resulting from solder reflow. In one embodiment, a solder-repellent surface is created adjacent to the solder to constrain the reflow and thereby maintain the vertical profile of the solder. Examples of such a solder-repellent surface include an oxide (such as Brown Oxide) of the lead frame, or a tape (such as Kapton) which is used as a dam bar to control/constrain the solder flow on the leads prior to the encapsulation step. In another embodiment, the solder connection may be formed from at least two components. The first component may reflow at high temperatures to provide the necessary adhesion between solder ball and the die, with the second component reflowing at a lower temperature to provide the necessary adhesion between the solder ball and the leads.

Abstract: A method of fabricating a large area, multi-element contactor. A segmented contactor is provided for testing semiconductor devices on a wafer that comprises a plurality of contactor units mounted to a substrate. The contactor units are formed, tested, and assembled to a backing substrate. The contactor units may include leads extending laterally for connection to an external instrument such as a burn-in board. The contactor units include conductive areas such as pads that are placed into contact with conductive terminals on devices under test.

Abstract: Embodiments in accordance with the present invention relate to flip-chip packages for semiconductor devices, which feature a die sandwiched between metal layers. One metal layer comprises portions of the lead frame configured to be in electrical and thermal communication with various pads on a first surface of the die (e.g. IC pads or MOSFET gate or source pads) through a solder ball contact. The other metal layer is configured to be in at least thermal communication with the opposite side of the die. Embodiments of packages in accordance with the present invention exhibit superior heat dissipation qualities, while avoiding the expense of wire bonding. Embodiments of the present invention are particularly suited for packaging of power devices.

Abstract: Embodiments in accordance with the present invention relate to techniques which avoid the problems of deformation in the shape of a solder connection in a flip chip package, resulting from solder reflow. In one embodiment, a solder-repellent surface is created adjacent to the solder to constrain the reflow and thereby maintain the vertical profile of the solder. Examples of such a solder-repellent surface include an oxide (such as Brown Oxide) of the lead frame, or a tape (such as Kapton) which is used as a dam bar to control/constrain the solder flow on the leads prior to the encapsulation step. In another embodiment, the solder connection may be formed from at least two components. The first component may reflow at high temperatures to provide the necessary adhesion between solder ball and the die, with the second component reflowing at a lower temperature to provide the necessary adhesion between the solder ball and the leads.

Abstract: Embodiments of the present invention relate to the use of stamping to form features on a lead frame of a semiconductor device package. In one embodiment, portions of the lead frame such as pins are moved out of the horizontal plane of a diepad by stamping. In certain embodiments, indentations or a complex cross-sectional profile, such as chamfered, may be imparted to portions of the pins and/or diepad by stamping. The complexity offered by such a stamped cross-sectional profile serves to enhance mechanical interlocking of the lead frame within the plastic molding of the package body. Other techniques such as selective electroplating and/or formation of a brown oxide guard band to limit spreading of adhesive material during die attach, may be employed alone or in combination to facilitate fabrication of a package having such stamped features.

Abstract: A method of fabricating a large area, multi-element contactor. A segmented contactor is provided for testing semiconductor devices on a wafer that comprises a plurality of contactor units mounted to a substrate. The contactor units are formed, tested, and assembled to a backing substrate. The contactor units may include leads extending laterally for connection to an external instrument such as a burn-in board. The contactor units include conductive areas such as pads that are placed into contact with conductive terminals on devices under test.

Abstract: A method of fabricating a large area, multi-element contactor. A segmented contactor is provided for testing semiconductor devices on a wafer that comprises a plurality of contactor units mounted to a substrate. The contactor units are formed, tested, and assembled to a backing substrate. The contactor units may include leads extending laterally for connection to an external instrument such as a burn-in board. The contactor units include conductive areas such as pads that are placed into contact with conductive terminals on devices under test.

Abstract: A method of fabricating a large area, multi-element contactor. A segmented contactor is provided for testing semiconductor devices on a wafer that comprises a plurality of contactor units mounted to a substrate. The contactor units are formed, tested, and assembled to a backing substrate. The contactor units may include leads extending laterally for connection to an external instrument such as a burn-in board. The contactor units include conductive areas such as pads that are placed into contact with conductive terminals on devices under test.

Abstract: A photodetector for power monitoring purposes may be positioned directly on a planar light circuit. The photodetector may be protected by hermetically sealing a localized region over the planar light circuit corresponding to the position of the photodetector. The remainder of the planar light circuit may remain unsealed.

Abstract: A method of fabricating a large area, multi-element contactor. A segmented contactor is provided for testing semiconductor devices on a wafer that comprises a plurality of contactor units mounted to a substrate. The contactor units are formed, tested, and assembled to a backing substrate. The contactor units may include leads extending laterally for connection to an external instrument such as a burn-in board. The contactor units include conductive areas such as pads that are placed into contact with conductive terminals on devices under test.

Abstract: A photodetector for power monitoring purposes may be positioned directly on a planar light circuit. The photodetector may be protected by hermetically sealing a localized region over the planar light circuit corresponding to the position of the photodetector. The remainder of the planar light circuit may remain unsealed.

Abstract: An improved structure for an organic ball-grid array chip carrier having an organic substrate attached to a metal heat sink plate to prevent the chip carrier from warping. A supplemental organic substrate is attached to the metal heat sink plate on the side opposite from the functional organic substrate to provide symmetry to the bending forces resulting from the mismatch in coefficients of thermal expansion between the organic substrate and the metal heat sink plate.

Abstract: A method of fabricating a large area, multi-element contactor. A segmented contactor is provided for testing semiconductor devices on a wafer that comprises a plurality of contactor units mounted to a substrate. The contactor units are formed, tested, and assembled to a backing substrate. The contactor units may include leads extending laterally for connection to an external instrument such as a burn-in board. The contactor units include conductive areas such as pads that are placed into contact with conductive terminals on devices under test.