Abstract: A generated-clock checker compares timing definitions against a register transfer level description of the design using formal methods. The generated-clock checker derives generated-clock timing waveform models from the timing definitions, derives generated-clock waveform models from the register level design and then compares the waveform models using formal methods.

Abstract: A generated-clock checker compares timing definitions against a register transfer level description of the design using formal methods. The generated-clock checker derives generated-clock timing waveform models from the timing definitions, derives generated-clock waveform models from the register level design and then compares the waveform models using formal methods.

Abstract: The circuit design process requires ways to reduce the power consumption of large integrated circuits and system-on-chip designs. This is typically done by introducing a process of clock gating thereby enabling or disabling flip-flops associated with specific functional blocks within the circuit. However, such changes in the circuit require synthesis and verification to ensure correctness of design and operation as sequential clock gating changes the state function dynamically. It is therefore necessary to define synthesis methods adapted to such dynamic changes in the design. According to an embodiment a sequential clock gating method uses an exclusive-OR technique to overcome the deficiencies of the prior art methods.

Abstract: A method of hybrid clock domain crossing (CDC) verification includes receiving a design or an integrated circuit (IC) design constraints. Static CDC verification is performed, including structural and functional verification. The result is checked and explicit or implicit assumptions are made to signoff verification. Incomplete formal analysis results are discarded after review. Assertions and monitors are generated by this process to capture the assumptions and check partially covered properties by formal analysis. A dynamic simulation is run using a testbench, the generated assertions and the monitors. The static verification and dynamic verification processes may be repeated until a satisfactory coverage is obtained. A system, such as a computer aided design (CAD) system, is configured to perform CDC verification of the IC design. The system may generate assertions and monitors to then run a simulation and determine coverage.

Abstract: A system and method enable strengthening of flip-Flops (FFs) in an integrated circuit (IC) for the purpose of reducing power consumption. This is achieved by using stability condition (STC) and observability don't-care (ODC) techniques. Strengthening enable is defined as ensuring that a FF later in the fan-out is enabled only when a FF earlier in the fan-out is driving a signal to that later FF. In an embodiment the fan-in of a FF is traversed and the STC or ODC is determined for the FF. Dependent on the determination a STC controller or an ODC controller is added to control the FF's enable signal. In an embodiment the power savings is checked and a controller is added only if there is a reduction in overall power consumption resulting from the addition of the controller.

Abstract: A system and method identify potentially static and/or quasi-static signals within an integrated circuit (IC), or portion thereof. Static and quasi-static signals may be identified in a design description of the IC by any one or more of: (1) a fan-out size exceeding some threshold, (2) a toggle frequency in a simulation trace that is below some threshold, and (3) a signal name that appears in a list accessed from the memory. Identification of static and quasi-static signals is performed, typically, as part of a verification process in order to flag cases where the verification system would otherwise indicate an error (e.g., at a clock domain crossing). Identifying a signal of the IC as being static or quasi-static improves the quality of results of verification and makes it easier for a prospective user to concentrate on actual rather than spurious issues reported during verification.

Abstract: A system and method enable strengthening of flip-Flops (FFs) in an integrated circuit (IC) for the purpose of reducing power consumption. This is achieved by using stability condition (STC) and observability don't-care (ODC) techniques. Strengthening enable is defined as ensuring that a FF later in the fan-out is enabled only when a FF earlier in the fan-out is driving a signal to that later FF. In an embodiment the fan-in of a FF is traversed and the STC or ODC is determined for the FF. Dependent on the determination a STC controller or an ODC controller is added to control the FF's enable signal. In an embodiment the power savings is checked and a controller is added only if there is a reduction in overall power consumption resulting from the addition of the controller.

Abstract: A method of hybrid clock domain crossing (CDC) verification includes receiving a design or an integrated circuit (IC) design constraints. Static CDC verification is performed, including structural and functional verification. The result is checked and explicit or implicit assumptions are made to signoff verification. Incomplete formal analysis results are discarded after review. Assertions and monitors are generated by this process to capture the assumptions and check partially covered properties by formal analysis. A dynamic simulation is run using a testbench, the generated assertions and the monitors. The static verification and dynamic verification processes may be repeated until a satisfactory coverage is obtained. A system, such as a computer aided design (CAD) system, is configured to perform CDC verification of the IC design. The system may generate assertions and monitors to then run a simulation and determine coverage.

Abstract: In order to realize some of the advantages described above, there is provided a computer system for verification of an intellectual property (IP) core in a system-on-chip (SoC). The system generates a plurality of verification specific abstracted views of the IP core, each of the plurality of verification specific abstracted views having a plurality of verification specific attributes at an input/output (I/O) interface of each of the abstracted view of the IP-core. A unified abstracted view of the IP-core is generated.

Abstract: In the process of designing an integrated circuit (IC), it is often the case that a functional description is converted into multiplexers. In some cases it would be more efficient to combine two or more multiplexers into a larger multiplexer to identify potential design problems in the original register transfer level (RTL). Such early detection can prevent routing congestion problem that would be too expensive to fix later. A large multiplexer is defined as a multiplexer having a number of inputs and control signals that is above a predetermined threshold. When such a multiplexing functionality is detected that function may be replaced in the circuit with a large multiplexer that would be a more efficient implementation. Accordingly the circuit is checked for existence of multiplexing functions, and merging, when possible, of such multiplexing functions to achieve the ability to instantiate the multiplexing functionality with a large multiplexer.

Abstract: In order to realize some of the advantages described above, there is provided a computer system for verification of an intellectual property (IP) core in a system-on-chip (SoC). The system generates a plurality of verification specific abstracted views of the IP core, each of the plurality of verification specific abstracted views having a plurality of verification specific attributes at an input/output (I/O) interface of each of the abstracted view of the IP-core. A unified abstracted view'of the IP-core is generated.

Abstract: The circuit design process requires ways to reduce the power consumption of large integrated circuits and system-on-chip designs. This is typically done by introducing a process of clock gating thereby enabling or disabling flip-flops associated with specific functional blocks within the circuit. However, such changes in the circuit require synthesis and verification to ensure correctness of design and operation as sequential clock gating changes the state function dynamically. It is therefore necessary to define synthesis methods adapted to such dynamic changes in the design. According to an embodiment a sequential clock gating method uses an exclusive-OR technique to overcome the deficiencies of the prior art methods.

Abstract: The circuit design process requires ways to reduce the power consumption of large integrated circuits and system-on-chip designs. This is typically done by introducing a process of clock gating thereby enabling or disabling flip-flops associated with specific functional blocks within the circuit. However, such changes in the circuit require synthesis and verification to ensure correctness of design and operation as sequential clock gating changes the state function dynamically. It is therefore necessary to define synthesis methods adapted to such dynamic changes in the design. According to an embodiment a sequential clock gating method uses an exclusive-OR technique to overcome the deficiencies of the prior art methods.

Abstract: In order to realize some of the advantages described above, there is provided a computer-implemented method for verification of an intellectual property (IP) core in a system-on-chip (SoC). The method comprises generating a plurality of verification specific abstracted views of the IP core each of the plurality of verification specific abstracted views having a plurality of verification specific attributes at an input/output (I/O) interface of each of the abstracted view of the IP-core. A unified abstracted view of the IP-core is generated.

Abstract: A method for generating timing exceptions for integrated circuit (IC) designs is disclosed. The method includes synthesizing an input RTL description into a gate-level netlist mapped to a technology library; detecting timing critical paths in the netlist; and determining for each detected timing critical path whether it induces timing exceptions. The timing exceptions generated by the disclosed method include, but are not limited to, multi-cycle paths, clock domain crossing false paths, asynchronous false paths, functional false paths, combinational false paths, sequential false paths, timing false paths, and the like.