Abstract: A vertically stacked 3D nanosheet field effect transistor component includes a bottom nanosheet device, a middle dielectric isolation region coupled to the bottom nanosheet device, and a top nanosheet device coupled to the middle dielectric isolation region. The middle dielectric isolation region can include at least one embedded stressor mechanically coupled to at least one of the bottom nanosheet device and the top nanosheet device that imparts an embedded stressor originated stress in at least one of the bottom nanosheet device and the top nanosheet device. At least one of the bottom nanosheet device and the top nanosheet device include at least one interlayer originated stress. The stress(es) impart device performance boost(s) for at least one of the bottom nanosheet device and the top nanosheet device.

Abstract: A semiconductor device includes a first transistor including a first drain region, and a second transistor including a second drain region, wherein in the second transistor is stacked over the first transistor. A contact structure is disposed through the second drain region, wherein the contact structure contacts the first drain region.

Abstract: A method of method of fabricating a semiconductor device includes providing a semiconductor structure having a sheet of vertically stacked formations including alternating semiconductor layers and sacrificial layers, surrounded by a layer of dummy gate material. The sacrificial layers are removed from the sheet leaving empty channels between the semiconductor layers. A gate oxide is deposited in the empty channels. The gate oxide wraps around the semiconductor layers in the sheet and defines layers of gate oxide. The layers of gate oxide are etched inward from a space between the vertically stacked formations, forming pockets between the layers of semiconductor. A dielectric spacer is deposited into the pockets. A source and drain formation is deposited into the space between the vertically stacked formations. The layer of dummy gate material is removed. The layers of gate oxide are removed. A gate is formed in contact with the semiconductor layers.

Abstract: A gate-all-around transistor includes a gate structure having sidewalls; a first and a second gate spacer positioned laterally on each sidewall, wherein the gate structure has a gate length between the sidewalls of the gate structure, the gate length having a midpoint; a first inner spacer under the first gate spacer; and a second inner spacer under the second gate spacer. A channel layer extends from below the first inner spacer, across the gate length to below the second inner spacer. The channel layer includes a first region having a first thickness and located below each of the gate spacers; and a second region having a continuously variable thickness, the second region located laterally between the first regions and being symmetrical in reference to the midpoint of the gate length.

Abstract: A semiconductor structure includes a first nanosheet field-effect transistor device having a plurality of first nanosheet channel layers disposed on a substrate, a second nanosheet field-effect transistor device adjacent the first field-effect transistor nanosheet device, the second field-effect transistor nanosheet device having a plurality of second nanosheet channel layers disposed on the substrate, a first source/drain region disposed between opposing sidewalls of the plurality of first nanosheet channel layers and the plurality of second nanosheet channel layers and extending into the substrate, and source/drain sidewall spacers disposed on sidewalls of the first source/drain region extending into the substrate.

Abstract: A semiconductor device includes a first stacked structure and a second stacked structure disposed on a substrate. The first stacked structure comprises a first plurality of gate structures alternately stacked with a first plurality of channel layers, and the second stacked structure comprises a second plurality of gate structures alternately stacked with a second plurality of channel layers. A first plurality of epitaxial source/drain regions are disposed on sides of the first stacked structure, and a second plurality of epitaxial source/drain regions are disposed on sides of the second stacked structure. A first dielectric layer is disposed between the first stacked structure and the substrate, and between the first plurality of epitaxial source/drain regions and the substrate. A second dielectric layer is disposed between the second stacked structure and the substrate. At least a portion of the second plurality of epitaxial source/drain regions contact the substrate.

Abstract: Methods for preventing fin bending in FinFET devices and related devices are provided. Embodiments include forming fins in a substrate; forming a non-conformal sacrificial layer over and between the fins to structurally conjoin the fins or an array of fins for structural integrity; forming a first gap-fill dielectric over the sacrificial layer and fins; recessing the first gap-fill dielectric to expose an upper portion of the fins and sacrificial layer; etching the sacrificial layer to expose the fins; forming a second gap-fill dielectric over the first gap-fill dielectric and over and between the fins; and recessing the second gap-fill dielectric to expose the upper portion of the fins.

Abstract: One aspect of the disclosure relates to a method of forming an integrated circuit structure. The method may include: forming a first work function metal over a set of fins having at least a first fin and a second fin; implanting the first work function metal with a first species; removing the implanted first work function metal from over the first fin such that a remaining portion of the implanted first work function metal remains over the second fin; forming a second work function metal over the set of fins including over the remaining portion of the implanted first work function metal; implanting the second work function metal with a second species; and forming a metal over the implanted second work function metal over the set of fins thereby forming the gate stack.

Abstract: One aspect of the disclosure relates to a method of forming an integrated circuit structure. The method may include: forming a first work function metal over a set of fins having at least a first fin and a second fin; implanting the first work function metal with a first species; removing the implanted first work function metal from over the first fin such that a remaining portion of the implanted first work function metal remains over the second fin; forming a second work function metal over the set of fins including over the remaining portion of the implanted first work function metal; implanting the second work function metal with a second species; and forming a metal over the implanted second work function metal over the set of fins thereby forming the gate stack.

Abstract: Methods of forming a semiconductor fin and methods for controlling dopant diffusion to a semiconductor fin are disclosed herein. The methods provide alternative ways to incorporate a carbon dopant into the fin to later control out-diffusion of dopants from a dopant-including epitaxial layer. One method includes depositing a carbon-containing layer over a portion of the fin adjacent to the gate and annealing to diffuse carbon from the carbon-containing layer into at least the portion of the semiconductor fin. This method can be applied to SOI or bulk semiconductor substrates. Another method includes epitaxially growing a carbon dopant containing semiconductor layer for later use in forming the fin.

Abstract: A method of forming a finFET structure having an ion implanted intermediate region next to the channel region of a finFET gate. The intermediate region is formed in a manner to reduce or eliminate migration of the dopant to undoped regions of the finFET thus forming abrupt finFET junction.

Abstract: A method of forming a finFET structure having an ion implanted intermediate region next to the channel region of a finFET gate. The intermediate region is formed in a manner to reduce or eliminate migration of the dopant to undoped regions of the finFET thus forming abrupt finFET junction.

Abstract: A semiconductor device fabrication process includes forming a fin upon a semiconductor substrate and forming a gate upon the semiconductor substrate and upon and orthogonal to the fin, forming a source drain contacts by growing epitaxy material over the fin, forming a trench between the epitaxy material and a gate to expose an upper surface portion of the fin, doping the exposed fin portion to form an extension region, and activating the extension region. The semiconductor device may include the fin, gate, gate spacers upon sidewalls of the gate, a source drain contact adjacent to the gate spacers surrounding the fin, and doped extension regions within the fin below the gate spacers.